70a64fe7b1
This extension does not appear to be on its way to ratification. Out of the unratified bitmanip extensions, this one had the largest impact on the compiler. Posting this patch to start a discussion about whether we should remove these extensions. We'll talk more at the RISC-V sync meeting this Thursday. Reviewed By: asb, reames Differential Revision: https://reviews.llvm.org/D133834
394 lines
11 KiB
LLVM
394 lines
11 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -target-abi=ilp32 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefixes=RV32,RV32I %s
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; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi=ilp32 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefixes=RV32,RV32IF %s
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; RUN: llc -mtriple=riscv64 -target-abi=lp64 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefixes=RV64,RV64I %s
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; RUN: llc -mtriple=riscv64 -mattr=+f,+d -target-abi=lp64 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefixes=RV64,RV64IFD %s
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;; This tests how good we are at materialising constants using `select`. The aim
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;; is that we do so without a branch if possible (at the moment our lowering of
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;; select always introduces a branch).
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;;
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;; Currently the hook `convertSelectOfConstantsToMath` only is useful when the
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;; constants are either 1 away from each other, or one is a power of two and
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;; the other is zero.
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define signext i32 @select_const_int_easy(i1 zeroext %a) nounwind {
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; RV32-LABEL: select_const_int_easy:
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; RV32: # %bb.0:
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; RV32-NEXT: ret
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;
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; RV64-LABEL: select_const_int_easy:
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; RV64: # %bb.0:
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; RV64-NEXT: ret
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%1 = select i1 %a, i32 1, i32 0
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ret i32 %1
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}
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define signext i32 @select_const_int_one_away(i1 zeroext %a) nounwind {
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; RV32-LABEL: select_const_int_one_away:
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; RV32: # %bb.0:
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; RV32-NEXT: li a1, 4
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; RV32-NEXT: sub a0, a1, a0
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; RV32-NEXT: ret
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;
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; RV64-LABEL: select_const_int_one_away:
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; RV64: # %bb.0:
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; RV64-NEXT: li a1, 4
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; RV64-NEXT: sub a0, a1, a0
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; RV64-NEXT: ret
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%1 = select i1 %a, i32 3, i32 4
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ret i32 %1
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}
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define signext i32 @select_const_int_pow2_zero(i1 zeroext %a) nounwind {
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; RV32-LABEL: select_const_int_pow2_zero:
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; RV32: # %bb.0:
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; RV32-NEXT: slli a0, a0, 2
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; RV32-NEXT: ret
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;
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; RV64-LABEL: select_const_int_pow2_zero:
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; RV64: # %bb.0:
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; RV64-NEXT: slli a0, a0, 2
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; RV64-NEXT: ret
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%1 = select i1 %a, i32 4, i32 0
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ret i32 %1
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}
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define signext i32 @select_const_int_harder(i1 zeroext %a) nounwind {
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; RV32-LABEL: select_const_int_harder:
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; RV32: # %bb.0:
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; RV32-NEXT: mv a1, a0
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; RV32-NEXT: li a0, 6
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; RV32-NEXT: bnez a1, .LBB3_2
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; RV32-NEXT: # %bb.1:
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; RV32-NEXT: li a0, 38
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; RV32-NEXT: .LBB3_2:
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; RV32-NEXT: ret
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;
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; RV64-LABEL: select_const_int_harder:
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; RV64: # %bb.0:
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; RV64-NEXT: mv a1, a0
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; RV64-NEXT: li a0, 6
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; RV64-NEXT: bnez a1, .LBB3_2
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; RV64-NEXT: # %bb.1:
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; RV64-NEXT: li a0, 38
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; RV64-NEXT: .LBB3_2:
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; RV64-NEXT: ret
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%1 = select i1 %a, i32 6, i32 38
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ret i32 %1
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}
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define float @select_const_fp(i1 zeroext %a) nounwind {
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; RV32I-LABEL: select_const_fp:
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; RV32I: # %bb.0:
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; RV32I-NEXT: mv a1, a0
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; RV32I-NEXT: lui a0, 263168
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; RV32I-NEXT: bnez a1, .LBB4_2
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; RV32I-NEXT: # %bb.1:
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; RV32I-NEXT: lui a0, 264192
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; RV32I-NEXT: .LBB4_2:
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; RV32I-NEXT: ret
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;
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; RV32IF-LABEL: select_const_fp:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: bnez a0, .LBB4_2
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; RV32IF-NEXT: # %bb.1:
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; RV32IF-NEXT: lui a0, %hi(.LCPI4_0)
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; RV32IF-NEXT: flw ft0, %lo(.LCPI4_0)(a0)
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; RV32IF-NEXT: fmv.x.w a0, ft0
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; RV32IF-NEXT: ret
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; RV32IF-NEXT: .LBB4_2:
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; RV32IF-NEXT: lui a0, %hi(.LCPI4_1)
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; RV32IF-NEXT: flw ft0, %lo(.LCPI4_1)(a0)
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; RV32IF-NEXT: fmv.x.w a0, ft0
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; RV32IF-NEXT: ret
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;
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; RV64I-LABEL: select_const_fp:
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; RV64I: # %bb.0:
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; RV64I-NEXT: mv a1, a0
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; RV64I-NEXT: lui a0, 263168
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; RV64I-NEXT: bnez a1, .LBB4_2
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; RV64I-NEXT: # %bb.1:
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; RV64I-NEXT: lui a0, 264192
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; RV64I-NEXT: .LBB4_2:
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; RV64I-NEXT: ret
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;
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; RV64IFD-LABEL: select_const_fp:
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; RV64IFD: # %bb.0:
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; RV64IFD-NEXT: bnez a0, .LBB4_2
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; RV64IFD-NEXT: # %bb.1:
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; RV64IFD-NEXT: lui a0, %hi(.LCPI4_0)
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; RV64IFD-NEXT: flw ft0, %lo(.LCPI4_0)(a0)
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; RV64IFD-NEXT: fmv.x.w a0, ft0
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; RV64IFD-NEXT: ret
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; RV64IFD-NEXT: .LBB4_2:
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; RV64IFD-NEXT: lui a0, %hi(.LCPI4_1)
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; RV64IFD-NEXT: flw ft0, %lo(.LCPI4_1)(a0)
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; RV64IFD-NEXT: fmv.x.w a0, ft0
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; RV64IFD-NEXT: ret
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%1 = select i1 %a, float 3.0, float 4.0
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ret float %1
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}
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define signext i32 @select_eq_zero_negone(i32 signext %a, i32 signext %b) nounwind {
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; RV32-LABEL: select_eq_zero_negone:
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; RV32: # %bb.0:
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; RV32-NEXT: xor a0, a0, a1
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; RV32-NEXT: snez a0, a0
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; RV32-NEXT: addi a0, a0, -1
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; RV32-NEXT: ret
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;
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; RV64-LABEL: select_eq_zero_negone:
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; RV64: # %bb.0:
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; RV64-NEXT: xor a0, a0, a1
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; RV64-NEXT: snez a0, a0
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; RV64-NEXT: addi a0, a0, -1
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; RV64-NEXT: ret
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%1 = icmp eq i32 %a, %b
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%2 = select i1 %1, i32 -1, i32 0
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ret i32 %2
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}
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define signext i32 @select_ne_zero_negone(i32 signext %a, i32 signext %b) nounwind {
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; RV32-LABEL: select_ne_zero_negone:
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; RV32: # %bb.0:
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; RV32-NEXT: xor a0, a0, a1
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; RV32-NEXT: seqz a0, a0
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; RV32-NEXT: addi a0, a0, -1
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; RV32-NEXT: ret
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;
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; RV64-LABEL: select_ne_zero_negone:
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; RV64: # %bb.0:
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; RV64-NEXT: xor a0, a0, a1
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; RV64-NEXT: seqz a0, a0
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; RV64-NEXT: addi a0, a0, -1
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; RV64-NEXT: ret
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%1 = icmp ne i32 %a, %b
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%2 = select i1 %1, i32 -1, i32 0
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ret i32 %2
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}
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define signext i32 @select_sgt_zero_negone(i32 signext %a, i32 signext %b) nounwind {
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; RV32-LABEL: select_sgt_zero_negone:
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; RV32: # %bb.0:
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; RV32-NEXT: slt a0, a1, a0
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; RV32-NEXT: neg a0, a0
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; RV32-NEXT: ret
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;
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; RV64-LABEL: select_sgt_zero_negone:
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; RV64: # %bb.0:
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; RV64-NEXT: slt a0, a1, a0
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; RV64-NEXT: neg a0, a0
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; RV64-NEXT: ret
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%1 = icmp sgt i32 %a, %b
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%2 = select i1 %1, i32 -1, i32 0
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ret i32 %2
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}
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define signext i32 @select_slt_zero_negone(i32 signext %a, i32 signext %b) nounwind {
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; RV32-LABEL: select_slt_zero_negone:
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; RV32: # %bb.0:
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; RV32-NEXT: slt a0, a0, a1
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; RV32-NEXT: neg a0, a0
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; RV32-NEXT: ret
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;
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; RV64-LABEL: select_slt_zero_negone:
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; RV64: # %bb.0:
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; RV64-NEXT: slt a0, a0, a1
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; RV64-NEXT: neg a0, a0
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; RV64-NEXT: ret
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%1 = icmp slt i32 %a, %b
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%2 = select i1 %1, i32 -1, i32 0
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ret i32 %2
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}
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define signext i32 @select_sge_zero_negone(i32 signext %a, i32 signext %b) nounwind {
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; RV32-LABEL: select_sge_zero_negone:
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; RV32: # %bb.0:
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; RV32-NEXT: slt a0, a0, a1
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; RV32-NEXT: addi a0, a0, -1
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; RV32-NEXT: ret
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;
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; RV64-LABEL: select_sge_zero_negone:
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; RV64: # %bb.0:
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; RV64-NEXT: slt a0, a0, a1
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; RV64-NEXT: addi a0, a0, -1
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; RV64-NEXT: ret
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%1 = icmp sge i32 %a, %b
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%2 = select i1 %1, i32 -1, i32 0
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ret i32 %2
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}
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define signext i32 @select_sle_zero_negone(i32 signext %a, i32 signext %b) nounwind {
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; RV32-LABEL: select_sle_zero_negone:
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; RV32: # %bb.0:
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; RV32-NEXT: slt a0, a1, a0
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; RV32-NEXT: addi a0, a0, -1
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; RV32-NEXT: ret
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;
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; RV64-LABEL: select_sle_zero_negone:
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; RV64: # %bb.0:
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; RV64-NEXT: slt a0, a1, a0
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; RV64-NEXT: addi a0, a0, -1
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; RV64-NEXT: ret
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%1 = icmp sle i32 %a, %b
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%2 = select i1 %1, i32 -1, i32 0
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ret i32 %2
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}
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define signext i32 @select_ugt_zero_negone(i32 signext %a, i32 signext %b) nounwind {
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; RV32-LABEL: select_ugt_zero_negone:
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; RV32: # %bb.0:
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; RV32-NEXT: sltu a0, a1, a0
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; RV32-NEXT: neg a0, a0
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; RV32-NEXT: ret
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;
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; RV64-LABEL: select_ugt_zero_negone:
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; RV64: # %bb.0:
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; RV64-NEXT: sltu a0, a1, a0
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; RV64-NEXT: neg a0, a0
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; RV64-NEXT: ret
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%1 = icmp ugt i32 %a, %b
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%2 = select i1 %1, i32 -1, i32 0
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ret i32 %2
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}
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define signext i32 @select_ult_zero_negone(i32 signext %a, i32 signext %b) nounwind {
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; RV32-LABEL: select_ult_zero_negone:
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; RV32: # %bb.0:
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; RV32-NEXT: sltu a0, a0, a1
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; RV32-NEXT: neg a0, a0
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; RV32-NEXT: ret
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;
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; RV64-LABEL: select_ult_zero_negone:
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; RV64: # %bb.0:
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; RV64-NEXT: sltu a0, a0, a1
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; RV64-NEXT: neg a0, a0
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; RV64-NEXT: ret
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%1 = icmp ult i32 %a, %b
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%2 = select i1 %1, i32 -1, i32 0
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ret i32 %2
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}
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define signext i32 @select_uge_zero_negone(i32 signext %a, i32 signext %b) nounwind {
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; RV32-LABEL: select_uge_zero_negone:
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; RV32: # %bb.0:
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; RV32-NEXT: sltu a0, a0, a1
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; RV32-NEXT: addi a0, a0, -1
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; RV32-NEXT: ret
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;
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; RV64-LABEL: select_uge_zero_negone:
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; RV64: # %bb.0:
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; RV64-NEXT: sltu a0, a0, a1
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; RV64-NEXT: addi a0, a0, -1
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; RV64-NEXT: ret
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%1 = icmp uge i32 %a, %b
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%2 = select i1 %1, i32 -1, i32 0
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ret i32 %2
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}
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define signext i32 @select_ule_zero_negone(i32 signext %a, i32 signext %b) nounwind {
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; RV32-LABEL: select_ule_zero_negone:
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; RV32: # %bb.0:
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; RV32-NEXT: sltu a0, a1, a0
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; RV32-NEXT: addi a0, a0, -1
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; RV32-NEXT: ret
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;
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; RV64-LABEL: select_ule_zero_negone:
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; RV64: # %bb.0:
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; RV64-NEXT: sltu a0, a1, a0
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; RV64-NEXT: addi a0, a0, -1
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; RV64-NEXT: ret
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%1 = icmp ule i32 %a, %b
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%2 = select i1 %1, i32 -1, i32 0
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ret i32 %2
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}
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define i32 @select_eq_1_2(i32 signext %a, i32 signext %b) {
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; RV32-LABEL: select_eq_1_2:
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; RV32: # %bb.0:
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; RV32-NEXT: xor a0, a0, a1
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; RV32-NEXT: snez a0, a0
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; RV32-NEXT: addi a0, a0, 1
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; RV32-NEXT: ret
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;
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; RV64-LABEL: select_eq_1_2:
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; RV64: # %bb.0:
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; RV64-NEXT: xor a0, a0, a1
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; RV64-NEXT: snez a0, a0
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; RV64-NEXT: addi a0, a0, 1
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; RV64-NEXT: ret
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%1 = icmp eq i32 %a, %b
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%2 = select i1 %1, i32 1, i32 2
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ret i32 %2
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}
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define i32 @select_ne_1_2(i32 signext %a, i32 signext %b) {
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; RV32-LABEL: select_ne_1_2:
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; RV32: # %bb.0:
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; RV32-NEXT: xor a0, a0, a1
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; RV32-NEXT: seqz a0, a0
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; RV32-NEXT: addi a0, a0, 1
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; RV32-NEXT: ret
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;
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; RV64-LABEL: select_ne_1_2:
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; RV64: # %bb.0:
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; RV64-NEXT: xor a0, a0, a1
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; RV64-NEXT: seqz a0, a0
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; RV64-NEXT: addi a0, a0, 1
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; RV64-NEXT: ret
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%1 = icmp ne i32 %a, %b
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%2 = select i1 %1, i32 1, i32 2
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ret i32 %2
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}
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define i32 @select_eq_10000_10001(i32 signext %a, i32 signext %b) {
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; RV32-LABEL: select_eq_10000_10001:
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; RV32: # %bb.0:
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; RV32-NEXT: xor a0, a0, a1
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; RV32-NEXT: seqz a0, a0
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; RV32-NEXT: lui a1, 2
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; RV32-NEXT: addi a1, a1, 1810
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; RV32-NEXT: sub a0, a1, a0
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; RV32-NEXT: ret
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;
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; RV64-LABEL: select_eq_10000_10001:
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; RV64: # %bb.0:
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; RV64-NEXT: xor a0, a0, a1
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; RV64-NEXT: seqz a0, a0
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; RV64-NEXT: lui a1, 2
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; RV64-NEXT: addiw a1, a1, 1810
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; RV64-NEXT: sub a0, a1, a0
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; RV64-NEXT: ret
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%1 = icmp eq i32 %a, %b
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%2 = select i1 %1, i32 10001, i32 10002
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ret i32 %2
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}
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define i32 @select_ne_10001_10002(i32 signext %a, i32 signext %b) {
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; RV32-LABEL: select_ne_10001_10002:
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; RV32: # %bb.0:
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; RV32-NEXT: xor a0, a0, a1
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; RV32-NEXT: snez a0, a0
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; RV32-NEXT: lui a1, 2
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; RV32-NEXT: addi a1, a1, 1810
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; RV32-NEXT: sub a0, a1, a0
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; RV32-NEXT: ret
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;
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; RV64-LABEL: select_ne_10001_10002:
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; RV64: # %bb.0:
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; RV64-NEXT: xor a0, a0, a1
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; RV64-NEXT: snez a0, a0
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; RV64-NEXT: lui a1, 2
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; RV64-NEXT: addiw a1, a1, 1810
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; RV64-NEXT: sub a0, a1, a0
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; RV64-NEXT: ret
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%1 = icmp ne i32 %a, %b
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%2 = select i1 %1, i32 10001, i32 10002
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ret i32 %2
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}
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