40e9284f3c
The instruction simplification will try to simplify the affected phis. In some cases, this might extend the liveness of values. For example: BB0: | \ | BB1 | / BB2:phi (BB0, v), (BB1, undef) The phi in BB2 will be simplified to v as v dominates BB2, but this is increasing the number of active values in BB1. By setting CanUseUndef to false, we will not simplify the phi in this way, this would help register pressure. This is mandatory for the later change to help reducing VGPR pressure for AMDGPU. Reviewed by: foad, sameerds Differential Revision: https://reviews.llvm.org/D132449
59 lines
2.3 KiB
LLVM
59 lines
2.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -S -structurizecfg %s -o - | FileCheck %s
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; CHECK-NOT: br i1 true
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define void @blam(i32 addrspace(1)* nocapture %arg, float %arg1, float %arg2) {
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; CHECK-LABEL: @blam(
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; CHECK-NEXT: bb:
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; CHECK-NEXT: br label [[BB3:%.*]]
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; CHECK: bb3:
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; CHECK-NEXT: [[TMP:%.*]] = phi i64 [ 0, [[BB:%.*]] ], [ [[TMP2:%.*]], [[FLOW1:%.*]] ]
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; CHECK-NEXT: [[TMP4:%.*]] = fcmp ult float [[ARG1:%.*]], 3.500000e+00
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; CHECK-NEXT: [[TMP4_INV:%.*]] = xor i1 [[TMP4]], true
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; CHECK-NEXT: br i1 [[TMP4_INV]], label [[BB5:%.*]], label [[FLOW:%.*]]
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; CHECK: bb5:
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; CHECK-NEXT: [[TMP6:%.*]] = fcmp uge float 0.000000e+00, [[ARG2:%.*]]
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; CHECK-NEXT: br label [[FLOW]]
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; CHECK: Flow:
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; CHECK-NEXT: [[TMP0:%.*]] = phi i32 [ 15, [[BB5]] ], [ undef, [[BB3]] ]
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; CHECK-NEXT: [[TMP1:%.*]] = phi i1 [ [[TMP6]], [[BB5]] ], [ [[TMP4]], [[BB3]] ]
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; CHECK-NEXT: br i1 [[TMP1]], label [[BB7:%.*]], label [[FLOW1]]
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; CHECK: bb7:
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; CHECK-NEXT: [[TMP8:%.*]] = add nuw nsw i64 [[TMP]], 1
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; CHECK-NEXT: [[TMP9:%.*]] = icmp sge i64 [[TMP8]], 5
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; CHECK-NEXT: br label [[FLOW1]]
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; CHECK: Flow1:
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; CHECK-NEXT: [[TMP2]] = phi i64 [ [[TMP8]], [[BB7]] ], [ undef, [[FLOW]] ]
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; CHECK-NEXT: [[TMP3:%.*]] = phi i32 [ 255, [[BB7]] ], [ [[TMP0]], [[FLOW]] ]
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; CHECK-NEXT: [[TMP4:%.*]] = phi i1 [ [[TMP9]], [[BB7]] ], [ true, [[FLOW]] ]
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; CHECK-NEXT: br i1 [[TMP4]], label [[BB10:%.*]], label [[BB3]]
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; CHECK: bb10:
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; CHECK-NEXT: store i32 [[TMP3]], i32 addrspace(1)* [[ARG:%.*]], align 4
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; CHECK-NEXT: ret void
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;
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bb:
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br label %bb3
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bb3: ; preds = %bb7, %bb
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%tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb7 ]
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%tmp4 = fcmp ult float %arg1, 3.500000e+00
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br i1 %tmp4, label %bb7, label %bb5
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bb5: ; preds = %bb3
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%tmp6 = fcmp olt float 0.000000e+00, %arg2
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br i1 %tmp6, label %bb10, label %bb7
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bb7: ; preds = %bb5, %bb3
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%tmp8 = add nuw nsw i64 %tmp, 1
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%tmp9 = icmp slt i64 %tmp8, 5
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br i1 %tmp9, label %bb3, label %bb10
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bb10: ; preds = %bb7, %bb5
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%tmp11 = phi i32 [ 15, %bb5 ], [ 255, %bb7 ]
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store i32 %tmp11, i32 addrspace(1)* %arg, align 4
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ret void
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}
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