Thomas Raoux 91594b5b98 [mlir][nvpu] Prevent F32ToTF32 pattern to generate illegal IR ...

We shouldn't apply this pattern to non F32->F32 mma.sync operations.

Differential Revision: https://reviews.llvm.org/D131902

2022-08-15 16:46:18 +00:00

..

invalid.mlir

[mlir][NVGPU] nvgpu.mmasync on F32 through TF32

2022-08-01 23:23:27 +00:00

mma-sync-f32-to-tf32.mlir

[mlir][nvpu] Prevent F32ToTF32 pattern to generate illegal IR

2022-08-15 16:46:18 +00:00

mma-sync-f32-to-tf32x3.mlir

[mlir][NVGPU] nvgpu.mmasync on F32 through TF32

2022-08-01 23:23:27 +00:00

optimize-shared-memory.mlir

[mlir][nvgpu] shared memory access optimization pass

2022-06-17 09:31:05 -06:00

roundtrip.mlir

[mlir][gpu] Move async copy ops to NVGPU and add caching hints

2022-05-10 22:30:24 +00:00