Aart Bik b430a352ef [mlir][sparse] use straightline and loop to insert into tensor ...

This exposed a missing type conversion for codegen

Reviewed By: Peiming

Differential Revision: https://reviews.llvm.org/D136286

2022-10-21 16:17:15 -07:00

..

Arith/CPU

[mlir][arith] Add shli support to WIE

2022-10-05 15:09:58 -04:00

Async/CPU

[MLIR] Switch lit tests to %mlir_lib_dir and %mlir_src_dir replacements.

2022-09-06 12:34:14 +02:00

Complex/CPU

[MLIR] Switch lit tests to %mlir_lib_dir and %mlir_src_dir replacements.

2022-09-06 12:34:14 +02:00

Linalg/CPU

[mlir][Linalg] Retire LinalgStrategyTilePass and filter-based pattern.

2022-10-11 02:42:56 -07:00

LLVMIR/CPU

[MLIR] Switch lit tests to %mlir_lib_dir and %mlir_src_dir replacements.

2022-09-06 12:34:14 +02:00

Memref

[mlir][NFC] Update textual references of func to func.func in Integration tests

2022-04-20 22:17:29 -07:00

PDL/CPU

[mlir:PDL] Fix a syntax ambiguity in pdl.attribute

2022-04-28 12:57:59 -07:00

SparseTensor

[mlir][sparse] use straightline and loop to insert into tensor

2022-10-21 16:17:15 -07:00

Standard/CPU

[MLIR] Switch lit tests to %mlir_lib_dir and %mlir_src_dir replacements.

2022-09-06 12:34:14 +02:00

Vector

[mlir][memref] Add realloc op.

2022-09-21 08:04:00 -07:00