David Green ab7110bcd6
[AArch64][SVE] Remove pseudo from LD1_IMM (#73631)
The LD1 immediate offset instructions have both a pseudo and a real
instruction, mostly as the instructions shares a tablegen class with the
FFR version of the instructions. As far as I can tell the pseudo for the
non-ffr versions does not serve any useful purpose though, and we can
rejig the the classes to only define the pseudo for FFR instructions
similar to the existing sve_mem_cld_ss instructions.

The end result of this is that we don't have a SideEffects flag on the
LD1_IMM instructions whilst scheduling them, and have a few less pseudo
instructions which is usually a good thing.
2023-11-28 12:13:26 +00:00
..
2023-01-24 22:36:39 +01:00
2023-03-23 20:20:20 -07:00
2023-08-08 21:59:53 +01:00
2023-01-24 22:36:39 +01:00

++ SVE CodeGen Warnings ++

When the WARN check lines fail in the SVE codegen tests it most likely means you
have introduced a warning due to:
1. Adding an invalid call to VectorType::getNumElements() or EVT::getVectorNumElements()
   when the type is a scalable vector.
2. Relying upon an implicit cast conversion from TypeSize to uint64_t.

For generic code, please modify your code to work with ElementCount and TypeSize directly.
For target-specific code that only deals with fixed-width vectors, use the fixed-size interfaces.
Please refer to the code where those functions live for more details.