llvm-project/llvm/test/CodeGen/AArch64/bsp_implicit_ops.mir
David Green 95201b2b64
[AArch64] Ensure we transferImpOps on BSP pseudo expansions. (#149456)
This ensures that we transfer implicit operands to the new expanded
pseudos if necessary, similarly to other pseudo expansions.
2025-07-22 08:10:34 +01:00

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass aarch64-expand-pseudo -verify-machineinstrs %s -o - | FileCheck %s
---
name: BSL_COPY
tracksRegLiveness: true
body: |
bb.0.entry:
liveins: $q20, $q21, $q22, $q23, $q6, $q1, $q7
; CHECK-LABEL: name: BSL_COPY
; CHECK: liveins: $q20, $q21, $q22, $q23, $q6, $q1, $q7
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: renamable $q2 = ORRv16i8 killed renamable $q20, killed renamable $q20
; CHECK-NEXT: renamable $q2 = BSLv16i8 killed renamable $q2, renamable $q21, renamable $q6, implicit killed $q21_q22_q23, implicit killed $q0_q1_q2_q3, implicit-def $q0_q1_q2_q3
; CHECK-NEXT: $q22 = ORRv16i8 $q0, killed $q0
; CHECK-NEXT: $q23 = ORRv16i8 $q1, killed $q1
; CHECK-NEXT: $q24 = ORRv16i8 $q2, killed $q2
; CHECK-NEXT: $q25 = ORRv16i8 $q3, killed $q3
; CHECK-NEXT: RET undef $lr, implicit $q22
renamable $q2 = BSPv16i8 killed renamable $q20, renamable $q21, renamable $q6, implicit killed $q21_q22_q23, implicit killed $q0_q1_q2_q3, implicit-def $q0_q1_q2_q3
$q22 = ORRv16i8 $q0, killed $q0
$q23 = ORRv16i8 $q1, killed $q1
$q24 = ORRv16i8 $q2, killed $q2
$q25 = ORRv16i8 $q3, killed $q3
RET_ReallyLR implicit $q22
...
---
name: BSL
tracksRegLiveness: true
body: |
bb.0.entry:
liveins: $q20, $q21, $q22, $q23, $q6, $q1, $q7
; CHECK-LABEL: name: BSL
; CHECK: liveins: $q20, $q21, $q22, $q23, $q6, $q1, $q7
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: renamable $q2 = BSLv16i8 killed renamable $q2, renamable $q21, renamable $q6, implicit killed $q21_q22_q23, implicit killed $q0_q1_q2_q3, implicit-def $q0_q1_q2_q3
; CHECK-NEXT: $q22 = ORRv16i8 $q0, killed $q0
; CHECK-NEXT: $q23 = ORRv16i8 $q1, killed $q1
; CHECK-NEXT: $q24 = ORRv16i8 $q2, killed $q2
; CHECK-NEXT: $q25 = ORRv16i8 $q3, killed $q3
; CHECK-NEXT: RET undef $lr, implicit $q22
renamable $q2 = BSPv16i8 killed renamable $q2, renamable $q21, renamable $q6, implicit killed $q21_q22_q23, implicit killed $q0_q1_q2_q3, implicit-def $q0_q1_q2_q3
$q22 = ORRv16i8 $q0, killed $q0
$q23 = ORRv16i8 $q1, killed $q1
$q24 = ORRv16i8 $q2, killed $q2
$q25 = ORRv16i8 $q3, killed $q3
RET_ReallyLR implicit $q22
...
---
name: BIF
tracksRegLiveness: true
body: |
bb.0.entry:
liveins: $q20, $q21, $q22, $q23, $q6, $q1, $q7
; CHECK-LABEL: name: BIF
; CHECK: liveins: $q20, $q21, $q22, $q23, $q6, $q1, $q7
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: renamable $q2 = BIFv16i8 renamable $q2, renamable $q6, killed renamable $q20, implicit killed $q21_q22_q23, implicit killed $q0_q1_q2_q3, implicit-def $q0_q1_q2_q3
; CHECK-NEXT: $q22 = ORRv16i8 $q0, killed $q0
; CHECK-NEXT: $q23 = ORRv16i8 $q1, killed $q1
; CHECK-NEXT: $q24 = ORRv16i8 $q2, killed $q2
; CHECK-NEXT: $q25 = ORRv16i8 $q3, killed $q3
; CHECK-NEXT: RET undef $lr, implicit $q22
renamable $q2 = BSPv16i8 killed renamable $q20, renamable $q2, renamable $q6, implicit killed $q21_q22_q23, implicit killed $q0_q1_q2_q3, implicit-def $q0_q1_q2_q3
$q22 = ORRv16i8 $q0, killed $q0
$q23 = ORRv16i8 $q1, killed $q1
$q24 = ORRv16i8 $q2, killed $q2
$q25 = ORRv16i8 $q3, killed $q3
RET_ReallyLR implicit $q22
...
---
name: BIT
tracksRegLiveness: true
body: |
bb.0.entry:
liveins: $q20, $q21, $q22, $q23, $q6, $q1, $q7
; CHECK-LABEL: name: BIT
; CHECK: liveins: $q20, $q21, $q22, $q23, $q6, $q1, $q7
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: renamable $q2 = BITv16i8 renamable $q2, renamable $q21, killed renamable $q20, implicit killed $q21_q22_q23, implicit killed $q0_q1_q2_q3, implicit-def $q0_q1_q2_q3
; CHECK-NEXT: $q22 = ORRv16i8 $q0, killed $q0
; CHECK-NEXT: $q23 = ORRv16i8 $q1, killed $q1
; CHECK-NEXT: $q24 = ORRv16i8 $q2, killed $q2
; CHECK-NEXT: $q25 = ORRv16i8 $q3, killed $q3
; CHECK-NEXT: RET undef $lr, implicit $q22
renamable $q2 = BSPv16i8 killed renamable $q20, renamable $q21, renamable $q2, implicit killed $q21_q22_q23, implicit killed $q0_q1_q2_q3, implicit-def $q0_q1_q2_q3
$q22 = ORRv16i8 $q0, killed $q0
$q23 = ORRv16i8 $q1, killed $q1
$q24 = ORRv16i8 $q2, killed $q2
$q25 = ORRv16i8 $q3, killed $q3
RET_ReallyLR implicit $q22
...