20d8398825
Whole wave functions are functions that will run with a full EXEC mask. They will not be invoked directly, but instead will be launched by way of a new intrinsic, `llvm.amdgcn.call.whole.wave` (to be added in a future patch). These functions are meant as an alternative to the `llvm.amdgcn.init.whole.wave` or `llvm.amdgcn.strict.wwm` intrinsics. Whole wave functions will set EXEC to -1 in the prologue and restore the original value of EXEC in the epilogue. They must have a special first argument, `i1 %active`, that is going to be mapped to EXEC. They may have either the default calling convention or amdgpu_gfx. The inactive lanes need to be preserved for all registers used, active lanes only for the CSRs. At the IR level, arguments to a whole wave function (other than `%active`) contain poison in their inactive lanes. Likewise, the return value for the inactive lanes is poison. This patch contains the following work: * 2 new pseudos, SI_SETUP_WHOLE_WAVE_FUNC and SI_WHOLE_WAVE_FUNC_RETURN used for managing the EXEC mask. SI_SETUP_WHOLE_WAVE_FUNC will return a SReg_1 representing `%active`, which needs to be passed into SI_WHOLE_WAVE_FUNC_RETURN. * SelectionDAG support for generating these 2 new pseudos and the special handling of %active. Since the return may be in a different basic block, it's difficult to add the virtual reg for %active to SI_WHOLE_WAVE_FUNC_RETURN, so we initially generate an IMPLICIT_DEF which is later replaced via a custom inserter. * Expansion of the 2 pseudos during prolog/epilog insertion. PEI also marks any used VGPRs as WWM registers, which are then spilled and restored with the usual logic. Future patches will include the `llvm.amdgcn.call.whole.wave` intrinsic and a lot of optimization work (especially in order to reduce spills around function calls). --------- Co-authored-by: Matt Arsenault <Matthew.Arsenault@amd.com> Co-authored-by: Shilei Tian <i@tianshilei.me>
65 lines
3.2 KiB
LLVM
65 lines
3.2 KiB
LLVM
; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -amdgpu-spill-sgpr-to-vgpr=0 -stop-after prologepilog -verify-machineinstrs %s -o - | FileCheck -check-prefix=AFTER-PEI %s
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; Test that the ScavengeFI is serialized in the SIMachineFunctionInfo.
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; AFTER-PEI-LABEL: {{^}}name: scavenge_fi
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; AFTER-PEI: machineFunctionInfo:
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; AFTER-PEI-NEXT: explicitKernArgSize: 12
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; AFTER-PEI-NEXT: maxKernArgAlign: 8
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; AFTER-PEI-NEXT: ldsSize: 0
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; AFTER-PEI-NEXT: gdsSize: 0
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; AFTER-PEI-NEXT: dynLDSAlign: 1
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; AFTER-PEI-NEXT: isEntryFunction: true
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; AFTER-PEI-NEXT: isChainFunction: false
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; AFTER-PEI-NEXT: noSignedZerosFPMath: false
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; AFTER-PEI-NEXT: memoryBound: false
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; AFTER-PEI-NEXT: waveLimiter: false
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; AFTER-PEI-NEXT: hasSpilledSGPRs: true
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; AFTER-PEI-NEXT: hasSpilledVGPRs: false
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; AFTER-PEI-NEXT: scratchRSrcReg: '$sgpr68_sgpr69_sgpr70_sgpr71'
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; AFTER-PEI-NEXT: frameOffsetReg: '$fp_reg'
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; AFTER-PEI-NEXT: stackPtrOffsetReg: '$sgpr32'
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; AFTER-PEI-NEXT: bytesInStackArgArea: 0
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; AFTER-PEI-NEXT: returnsVoid: true
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; AFTER-PEI-NEXT: argumentInfo:
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; AFTER-PEI-NEXT: privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' }
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; AFTER-PEI-NEXT: kernargSegmentPtr: { reg: '$sgpr4_sgpr5' }
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; AFTER-PEI-NEXT: workGroupIDX: { reg: '$sgpr6' }
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; AFTER-PEI-NEXT: privateSegmentWaveByteOffset: { reg: '$sgpr7' }
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; AFTER-PEI-NEXT: workItemIDX: { reg: '$vgpr0' }
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; AFTER-PEI-NEXT: psInputAddr: 0
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; AFTER-PEI-NEXT: psInputEnable: 0
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; AFTER-PEI-NEXT: maxMemoryClusterDWords: 8
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; AFTER-PEI-NEXT: mode:
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; AFTER-PEI-NEXT: ieee: true
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; AFTER-PEI-NEXT: dx10-clamp: true
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; AFTER-PEI-NEXT: fp32-input-denormals: true
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; AFTER-PEI-NEXT: fp32-output-denormals: true
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; AFTER-PEI-NEXT: fp64-fp16-input-denormals: true
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; AFTER-PEI-NEXT: fp64-fp16-output-denormals: true
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; AFTER-PEI-NEXT: highBitsOf32BitAddress: 0
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; AFTER-PEI-NEXT: occupancy: 5
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; AFTER-PEI-NEXT: scavengeFI: '%stack.3'
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; AFTER-PEI-NEXT: vgprForAGPRCopy: ''
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; AFTER-PEI-NEXT: sgprForEXECCopy: ''
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; AFTER-PEI-NEXT: longBranchReservedReg: ''
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; AFTER-PEI-NEXT: hasInitWholeWave: false
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; AFTER-PEI-NEXT: dynamicVGPRBlockSize: 0
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; AFTER-PEI-NEXT: scratchReservedForDynamicVGPRs: 0
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; AFTER-PEI-NEXT: isWholeWaveFunction: false
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; AFTER-PEI-NEXT: body:
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define amdgpu_kernel void @scavenge_fi(ptr addrspace(1) %out, i32 %in) #0 {
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%wide.sgpr0 = call <32 x i32> asm sideeffect "; def $0", "=s" () #0
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%wide.sgpr1 = call <32 x i32> asm sideeffect "; def $0", "=s" () #0
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%wide.sgpr2 = call <32 x i32> asm sideeffect "; def $0", "=s" () #0
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%wide.sgpr3 = call <32 x i32> asm sideeffect "; def $0", "=s" () #0
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call void asm sideeffect "; use $0", "s"(<32 x i32> %wide.sgpr0) #0
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call void asm sideeffect "; use $0", "s"(<32 x i32> %wide.sgpr1) #0
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call void asm sideeffect "; use $0", "s"(<32 x i32> %wide.sgpr2) #0
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call void asm sideeffect "; use $0", "s"(<32 x i32> %wide.sgpr3) #0
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ret void
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}
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attributes #0 = { nounwind "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" }
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