shylie/llvm-project
1
0
Fork 0
Code Issues Pull Requests Actions 6 Packages Projects Releases Wiki Activity
llvm-project/llvm/test/Transforms/LoopVectorize/RISCV
History
Mel Chen 86916ff0f0
[LV] Fix gap mask requirement for interleaved access (#151105) 
When interleaved stores contain gaps, a mask is required to skip the
gaps, regardless of whether scalar epilogues are allowed.
This patch corrects the condition under which a gap mask is needed,
ensuring consistency between the legacy and VPlan-based cost models and
avoiding assertion failures.

Related #149981
2025-08-01 14:24:30 +08:00
..
bf16.ll
[RISCV][LV] Merge check lines in bf16/f16 tests. NFC
2025-08-01 11:26:16 +08:00
blend-any-of-reduction-cost.ll
[LLVM][IRBuilder] Use NUW arithmetic for Create{ElementCount,TypeSize}. (#143532)
2025-06-19 13:24:39 +01:00
blocks-with-dead-instructions.ll
[VPlan] Remove VPVectorPointer for part 0 after unrolling. (#149735)
2025-07-27 13:53:26 +01:00
dead-ops-cost.ll
[VPlan] Remove VPVectorPointer for part 0 after unrolling. (#149735)
2025-07-27 13:53:26 +01:00
defaults.ll
[VPlan] Remove VPVectorPointer for part 0 after unrolling. (#149735)
2025-07-27 13:53:26 +01:00
divrem.ll
[VPlan] Remove VPVectorPointer for part 0 after unrolling. (#149735)
2025-07-27 13:53:26 +01:00
evl-compatible-loops.ll
[VPlan] Create AVL as a phi from TC -> 0 with EVL tail folding (#151481)
2025-08-01 11:00:05 +08:00
evl-iv-simplify.ll
[LV][EVL] Introduce the EVLIndVarSimplify Pass for EVL-vectorized loops (#131005)
2025-05-14 13:49:50 -07:00
f16.ll
[RISCV][LV] Merge check lines in bf16/f16 tests. NFC
2025-08-01 11:26:16 +08:00
first-order-recurrence-scalable-vf1.ll
[VPlan] Remove VPVectorPointer for part 0 after unrolling. (#149735)
2025-07-27 13:53:26 +01:00
fminimumnum.ll
[VPlan] Remove VPVectorPointer for part 0 after unrolling. (#149735)
2025-07-27 13:53:26 +01:00
force-vect-msg.ll
[RISCV] Remove -riscv-v-vector-bits-min from LoopVectorize tests. NFC (#148565)
2025-07-14 21:59:35 +08:00
illegal-type.ll
[VPlan] Don't access canonical IV in VPWidenPointerInduction::execute.
2025-03-15 21:32:48 +00:00
induction-costs.ll
[LLVM][IRBuilder] Use NUW arithmetic for Create{ElementCount,TypeSize}. (#143532)
2025-06-19 13:24:39 +01:00
inloop-reduction.ll
[VPlan] Create AVL as a phi from TC -> 0 with EVL tail folding (#151481)
2025-08-01 11:00:05 +08:00
interleaved-accesses-zve32x.ll
…
interleaved-accesses.ll
[VPlan] Remove VPVectorPointer for part 0 after unrolling. (#149735)
2025-07-27 13:53:26 +01:00
interleaved-cost.ll
[RISCV] Add +optimized-nfN-segment-load-store (#114414)
2024-11-04 06:43:58 +08:00
interleaved-masked-access.ll
[VPlan] Create AVL as a phi from TC -> 0 with EVL tail folding (#151481)
2025-08-01 11:00:05 +08:00
interleaved-store-with-gap.ll
[LV] Fix gap mask requirement for interleaved access (#151105)
2025-08-01 14:24:30 +08:00
lit.local.cfg
…
lmul.ll
[VPlan] Remove VPVectorPointer for part 0 after unrolling. (#149735)
2025-07-27 13:53:26 +01:00
low-trip-count.ll
[VPlan] Remove VPVectorPointer for part 0 after unrolling. (#149735)
2025-07-27 13:53:26 +01:00
mask-index-type.ll
[VPlan] Remove VPVectorPointer for part 0 after unrolling. (#149735)
2025-07-27 13:53:26 +01:00
masked_gather_scatter.ll
[RISCV] Remove -riscv-v-vector-bits-min from LoopVectorize tests. NFC (#148565)
2025-07-14 21:59:35 +08:00
only-compute-cost-for-vplan-vfs.ll
[RISCV][LV] Use predicate-else-scalar-epilogue flag in tail folding tests. NFC
2025-07-28 17:04:00 +08:00
ordered-reduction.ll
[VPlan] Remove VPVectorPointer for part 0 after unrolling. (#149735)
2025-07-27 13:53:26 +01:00
partial-reduce-dot-product.ll
[VPlan] Remove VPVectorPointer for part 0 after unrolling. (#149735)
2025-07-27 13:53:26 +01:00
pr87378-vpinstruction-or-drop-poison-generating-flags.ll
[VPlan] Remove VPVectorPointer for part 0 after unrolling. (#149735)
2025-07-27 13:53:26 +01:00
pr88802.ll
[VPlan] Create AVL as a phi from TC -> 0 with EVL tail folding (#151481)
2025-08-01 11:00:05 +08:00
preserve-dbg-loc.ll
[RISCV][LV] Use predicate-else-scalar-epilogue flag in tail folding tests. NFC
2025-07-28 17:04:00 +08:00
reductions.ll
[LV][RISCV] Regenerate reduction tests with UTC. NFC
2025-08-01 12:32:14 +08:00
reg-usage-bf16.ll
[LV] Fix MVE regression from #132190 (#141736)
2025-06-16 09:58:03 +01:00
reg-usage-f16.ll
[LV] Fix MVE regression from #132190 (#141736)
2025-06-16 09:58:03 +01:00
reg-usage.ll
[RISCV] Remove -riscv-v-vector-bits-min from LoopVectorize tests. NFC (#148565)
2025-07-14 21:59:35 +08:00
remark-reductions.ll
[LLVM][IRBuilder] Use NUW arithmetic for Create{ElementCount,TypeSize}. (#143532)
2025-06-19 13:24:39 +01:00
riscv-interleaved.ll
[RISCV] Remove -riscv-v-vector-bits-min from LoopVectorize tests. NFC (#148565)
2025-07-14 21:59:35 +08:00
riscv-unroll.ll
[VPlan] Remove VPVectorPointer for part 0 after unrolling. (#149735)
2025-07-27 13:53:26 +01:00
riscv-vector-reverse.ll
[VPlan] Materialize constant vector trip counts before final opts. (#142309)
2025-07-26 17:16:36 +01:00
safe-dep-distance.ll
[VPlan] Remove VPVectorPointer for part 0 after unrolling. (#149735)
2025-07-27 13:53:26 +01:00
scalable-basics.ll
[VPlan] Remove VPVectorPointer for part 0 after unrolling. (#149735)
2025-07-27 13:53:26 +01:00
scalable-tailfold.ll
[VPlan] Create AVL as a phi from TC -> 0 with EVL tail folding (#151481)
2025-08-01 11:00:05 +08:00
scalable-vf-hint.ll
…
select-cmp-reduction.ll
[LV][RISCV] Regenerate select-cmp-reduction.ll with UTC. NFC
2025-08-01 12:38:18 +08:00
select-invariant-cond-cost.ll
[VPlan] Also check if plan for best legacy VF contains simplifications.
2024-11-08 20:53:03 +00:00
short-trip-count.ll
[VPlan] Remove VPVectorPointer for part 0 after unrolling. (#149735)
2025-07-27 13:53:26 +01:00
strided-accesses.ll
[VPlan] Remove VPVectorPointer for part 0 after unrolling. (#149735)
2025-07-27 13:53:26 +01:00
tail-folding-bin-unary-ops-args.ll
[VPlan] Create AVL as a phi from TC -> 0 with EVL tail folding (#151481)
2025-08-01 11:00:05 +08:00
tail-folding-call-intrinsics.ll
[VPlan] Create AVL as a phi from TC -> 0 with EVL tail folding (#151481)
2025-08-01 11:00:05 +08:00
tail-folding-cast-intrinsics.ll
[VPlan] Create AVL as a phi from TC -> 0 with EVL tail folding (#151481)
2025-08-01 11:00:05 +08:00
tail-folding-cond-reduction.ll
[VPlan] Create AVL as a phi from TC -> 0 with EVL tail folding (#151481)
2025-08-01 11:00:05 +08:00
tail-folding-cost.ll
[RISCV][LV] Remove redundant -force-tail-folding-style from tests. NFC
2025-07-28 16:11:01 +08:00
tail-folding-div.ll
[VPlan] Create AVL as a phi from TC -> 0 with EVL tail folding (#151481)
2025-08-01 11:00:05 +08:00
tail-folding-fixed-order-recurrence.ll
[VPlan] Create AVL as a phi from TC -> 0 with EVL tail folding (#151481)
2025-08-01 11:00:05 +08:00
tail-folding-gather-scatter.ll
[VPlan] Create AVL as a phi from TC -> 0 with EVL tail folding (#151481)
2025-08-01 11:00:05 +08:00
tail-folding-inloop-reduction.ll
[VPlan] Create AVL as a phi from TC -> 0 with EVL tail folding (#151481)
2025-08-01 11:00:05 +08:00
tail-folding-interleave.ll
[VPlan] Create AVL as a phi from TC -> 0 with EVL tail folding (#151481)
2025-08-01 11:00:05 +08:00
tail-folding-intermediate-store.ll
[VPlan] Create AVL as a phi from TC -> 0 with EVL tail folding (#151481)
2025-08-01 11:00:05 +08:00
tail-folding-iv32.ll
[VPlan] Create AVL as a phi from TC -> 0 with EVL tail folding (#151481)
2025-08-01 11:00:05 +08:00
tail-folding-known-no-overflow.ll
[VPlan] Create AVL as a phi from TC -> 0 with EVL tail folding (#151481)
2025-08-01 11:00:05 +08:00
tail-folding-masked-loadstore.ll
[VPlan] Create AVL as a phi from TC -> 0 with EVL tail folding (#151481)
2025-08-01 11:00:05 +08:00
tail-folding-no-masking.ll
[RISCV][LV] Use predicate-else-scalar-epilogue flag in tail folding tests. NFC
2025-07-28 17:04:00 +08:00
tail-folding-ordered-reduction.ll
[VPlan] Create AVL as a phi from TC -> 0 with EVL tail folding (#151481)
2025-08-01 11:00:05 +08:00
tail-folding-reduction-cost.ll
[RISCV][LV] Use predicate-else-scalar-epilogue flag in tail folding tests. NFC
2025-07-28 17:04:00 +08:00
tail-folding-reduction.ll
[VPlan] Create AVL as a phi from TC -> 0 with EVL tail folding (#151481)
2025-08-01 11:00:05 +08:00
tail-folding-reverse-load-store.ll
[VPlan] Create AVL as a phi from TC -> 0 with EVL tail folding (#151481)
2025-08-01 11:00:05 +08:00
tail-folding-safe-dep-distance.ll
[VPlan] Create AVL as a phi from TC -> 0 with EVL tail folding (#151481)
2025-08-01 11:00:05 +08:00
tail-folding-uniform-store.ll
[VPlan] Create AVL as a phi from TC -> 0 with EVL tail folding (#151481)
2025-08-01 11:00:05 +08:00
truncate-to-minimal-bitwidth-cost.ll
[VPlan] Create AVL as a phi from TC -> 0 with EVL tail folding (#151481)
2025-08-01 11:00:05 +08:00
truncate-to-minimal-bitwidth-evl-crash.ll
[VPlan] Create AVL as a phi from TC -> 0 with EVL tail folding (#151481)
2025-08-01 11:00:05 +08:00
type-info-cache-evl-crash.ll
[VPlan] Create AVL as a phi from TC -> 0 with EVL tail folding (#151481)
2025-08-01 11:00:05 +08:00
uniform-load-store.ll
[VPlan] Create AVL as a phi from TC -> 0 with EVL tail folding (#151481)
2025-08-01 11:00:05 +08:00
unroll-in-loop-vectorizer.ll
[RISCV] Remove -riscv-v-vector-bits-min from LoopVectorize tests. NFC (#148565)
2025-07-14 21:59:35 +08:00
veclib-function-calls.ll
[RISCV][SLEEF]: Support SLEEF vector library for RISC-V target. (#114014)
2024-11-26 12:25:54 +03:00
vector-loop-backedge-elimination-with-evl.ll
[VPlan] Convert EVL loops to variable-length stepping after dissolution (#147222)
2025-07-30 16:50:57 +08:00
vectorize-vp-intrinsics.ll
[VPlan] Create AVL as a phi from TC -> 0 with EVL tail folding (#151481)
2025-08-01 11:00:05 +08:00
vf-will-not-generate-any-vector-insts.ll
[VPlan] Materialize constant vector trip counts before final opts. (#142309)
2025-07-26 17:16:36 +01:00
vplan-riscv-vector-reverse.ll
[NFC][LV] Refine the lit test case riscv-vector-reverse.ll (#149020)
2025-07-22 14:56:14 +08:00
vplan-vp-call-intrinsics.ll
[VPlan] Create AVL as a phi from TC -> 0 with EVL tail folding (#151481)
2025-08-01 11:00:05 +08:00
vplan-vp-cast-intrinsics.ll
[VPlan] Create AVL as a phi from TC -> 0 with EVL tail folding (#151481)
2025-08-01 11:00:05 +08:00
vplan-vp-intrinsics-fixed-order-recurrence.ll
[VPlan] Create AVL as a phi from TC -> 0 with EVL tail folding (#151481)
2025-08-01 11:00:05 +08:00
vplan-vp-intrinsics-reduction.ll
[VPlan] Create AVL as a phi from TC -> 0 with EVL tail folding (#151481)
2025-08-01 11:00:05 +08:00
vplan-vp-intrinsics.ll
[VPlan] Create AVL as a phi from TC -> 0 with EVL tail folding (#151481)
2025-08-01 11:00:05 +08:00
zvl32b.ll
…