d9b4bdbff5
The existing analysis was already a pimpl wrapper. I have extracted legacy pass logic to a LDVImpl wrapper named `LiveDebugVariables` which is the analysis::Result now. This controls whether to activate the LDV (depending on `-live-debug-variables` and DIsubprogram) itself. The legacy and new analysis only construct the LiveDebugVariables. VirtRegRewriter will test this.
119 lines
4.3 KiB
C++
119 lines
4.3 KiB
C++
//===- RISCVDeadRegisterDefinitions.cpp - Replace dead defs w/ zero reg --===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===---------------------------------------------------------------------===//
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//
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// This pass rewrites Rd to x0 for instrs whose return values are unused.
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//
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//===---------------------------------------------------------------------===//
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#include "RISCV.h"
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#include "RISCVSubtarget.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/LiveDebugVariables.h"
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#include "llvm/CodeGen/LiveIntervals.h"
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#include "llvm/CodeGen/LiveStacks.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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using namespace llvm;
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#define DEBUG_TYPE "riscv-dead-defs"
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#define RISCV_DEAD_REG_DEF_NAME "RISC-V Dead register definitions"
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STATISTIC(NumDeadDefsReplaced, "Number of dead definitions replaced");
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namespace {
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class RISCVDeadRegisterDefinitions : public MachineFunctionPass {
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public:
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static char ID;
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RISCVDeadRegisterDefinitions() : MachineFunctionPass(ID) {}
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bool runOnMachineFunction(MachineFunction &MF) override;
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.setPreservesCFG();
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AU.addRequired<LiveIntervalsWrapperPass>();
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AU.addPreserved<LiveIntervalsWrapperPass>();
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AU.addRequired<LiveIntervalsWrapperPass>();
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AU.addPreserved<SlotIndexesWrapperPass>();
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AU.addPreserved<LiveDebugVariablesWrapperLegacy>();
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AU.addPreserved<LiveStacks>();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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StringRef getPassName() const override { return RISCV_DEAD_REG_DEF_NAME; }
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};
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} // end anonymous namespace
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char RISCVDeadRegisterDefinitions::ID = 0;
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INITIALIZE_PASS(RISCVDeadRegisterDefinitions, DEBUG_TYPE,
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RISCV_DEAD_REG_DEF_NAME, false, false)
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FunctionPass *llvm::createRISCVDeadRegisterDefinitionsPass() {
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return new RISCVDeadRegisterDefinitions();
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}
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bool RISCVDeadRegisterDefinitions::runOnMachineFunction(MachineFunction &MF) {
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if (skipFunction(MF.getFunction()))
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return false;
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const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
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const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
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LiveIntervals &LIS = getAnalysis<LiveIntervalsWrapperPass>().getLIS();
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LLVM_DEBUG(dbgs() << "***** RISCVDeadRegisterDefinitions *****\n");
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bool MadeChange = false;
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for (MachineBasicBlock &MBB : MF) {
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for (MachineInstr &MI : MBB) {
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// We only handle non-computational instructions since some NOP encodings
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// are reserved for HINT instructions.
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const MCInstrDesc &Desc = MI.getDesc();
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if (!Desc.mayLoad() && !Desc.mayStore() &&
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!Desc.hasUnmodeledSideEffects() &&
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MI.getOpcode() != RISCV::PseudoVSETVLI &&
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MI.getOpcode() != RISCV::PseudoVSETIVLI)
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continue;
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// For PseudoVSETVLIX0, Rd = X0 has special meaning.
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if (MI.getOpcode() == RISCV::PseudoVSETVLIX0)
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continue;
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for (int I = 0, E = Desc.getNumDefs(); I != E; ++I) {
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MachineOperand &MO = MI.getOperand(I);
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if (!MO.isReg() || !MO.isDef() || MO.isEarlyClobber())
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continue;
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// Be careful not to change the register if it's a tied operand.
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if (MI.isRegTiedToUseOperand(I)) {
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LLVM_DEBUG(dbgs() << " Ignoring, def is tied operand.\n");
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continue;
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}
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Register Reg = MO.getReg();
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if (!Reg.isVirtual() || !MO.isDead())
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continue;
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LLVM_DEBUG(dbgs() << " Dead def operand #" << I << " in:\n ";
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MI.print(dbgs()));
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Register X0Reg;
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const TargetRegisterClass *RC = TII->getRegClass(Desc, I, TRI, MF);
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if (RC && RC->contains(RISCV::X0)) {
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X0Reg = RISCV::X0;
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} else if (RC && RC->contains(RISCV::X0_W)) {
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X0Reg = RISCV::X0_W;
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} else if (RC && RC->contains(RISCV::X0_H)) {
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X0Reg = RISCV::X0_H;
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} else {
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LLVM_DEBUG(dbgs() << " Ignoring, register is not a GPR.\n");
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continue;
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}
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assert(LIS.hasInterval(Reg));
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LIS.removeInterval(Reg);
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MO.setReg(X0Reg);
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LLVM_DEBUG(dbgs() << " Replacing with zero register. New:\n ";
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MI.print(dbgs()));
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++NumDeadDefsReplaced;
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MadeChange = true;
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}
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}
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}
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return MadeChange;
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}
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