17bfc00f7c
As discussed in [1], introduce BPF instructions with load-acquire and
store-release semantics under -mcpu=v4. Define 2 new flags:
BPF_LOAD_ACQ 0x100
BPF_STORE_REL 0x110
A "load-acquire" is a BPF_STX | BPF_ATOMIC instruction with the 'imm'
field set to BPF_LOAD_ACQ (0x100).
Similarly, a "store-release" is a BPF_STX | BPF_ATOMIC instruction with
the 'imm' field set to BPF_STORE_REL (0x110).
Unlike existing atomic read-modify-write operations that only support
BPF_W (32-bit) and BPF_DW (64-bit) size modifiers, load-acquires and
store-releases also support BPF_B (8-bit) and BPF_H (16-bit). An 8- or
16-bit load-acquire zero-extends the value before writing it to a 32-bit
register, just like ARM64 instruction LDAPRH and friends.
As an example (assuming little-endian):
long foo(long *ptr) {
return __atomic_load_n(ptr, __ATOMIC_ACQUIRE);
}
foo() can be compiled to:
db 10 00 00 00 01 00 00 r0 = load_acquire((u64 *)(r1 + 0x0))
95 00 00 00 00 00 00 00 exit
opcode (0xdb): BPF_ATOMIC | BPF_DW | BPF_STX
imm (0x00000100): BPF_LOAD_ACQ
Similarly:
void bar(short *ptr, short val) {
__atomic_store_n(ptr, val, __ATOMIC_RELEASE);
}
bar() can be compiled to:
cb 21 00 00 10 01 00 00 store_release((u16 *)(r1 + 0x0), w2)
95 00 00 00 00 00 00 00 exit
opcode (0xcb): BPF_ATOMIC | BPF_H | BPF_STX
imm (0x00000110): BPF_STORE_REL
Inline assembly is also supported.
Add a pre-defined macro, __BPF_FEATURE_LOAD_ACQ_STORE_REL, to let
developers detect this new feature. It can also be disabled using a new
llc option, -disable-load-acq-store-rel.
Using __ATOMIC_RELAXED for __atomic_store{,_n}() will generate a "plain"
store (BPF_MEM | BPF_STX) instruction:
void foo(short *ptr, short val) {
__atomic_store_n(ptr, val, __ATOMIC_RELAXED);
}
6b 21 00 00 00 00 00 00 *(u16 *)(r1 + 0x0) = w2
95 00 00 00 00 00 00 00 exit
Similarly, using __ATOMIC_RELAXED for __atomic_load{,_n}() will generate
a zero-extending, "plain" load (BPF_MEM | BPF_LDX) instruction:
int foo(char *ptr) {
return __atomic_load_n(ptr, __ATOMIC_RELAXED);
}
71 11 00 00 00 00 00 00 w1 = *(u8 *)(r1 + 0x0)
bc 10 08 00 00 00 00 00 w0 = (s8)w1
95 00 00 00 00 00 00 00 exit
Currently __ATOMIC_CONSUME is an alias for __ATOMIC_ACQUIRE. Using
__ATOMIC_SEQ_CST ("sequentially consistent") is not supported yet and
will cause an error:
$ clang --target=bpf -mcpu=v4 -c bar.c > /dev/null
bar.c:1:5: error: sequentially consistent (seq_cst) atomic load/store is
not supported
1 | int foo(int *ptr) { return __atomic_load_n(ptr, __ATOMIC_SEQ_CST); }
| ^
...
Finally, rename those isST*() and isLD*() helper functions in
BPFMISimplifyPatchable.cpp based on what the instructions actually do,
rather than their instruction class.
[1]
https://lore.kernel.org/all/20240729183246.4110549-1-yepeilin@google.com/
108 lines
3.2 KiB
C++
108 lines
3.2 KiB
C++
//===--- BPF.cpp - Implement BPF target feature support -------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements BPF TargetInfo objects.
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//
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//===----------------------------------------------------------------------===//
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#include "BPF.h"
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#include "Targets.h"
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#include "clang/Basic/MacroBuilder.h"
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#include "clang/Basic/TargetBuiltins.h"
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#include "llvm/ADT/StringRef.h"
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using namespace clang;
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using namespace clang::targets;
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static constexpr int NumBuiltins =
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clang::BPF::LastTSBuiltin - Builtin::FirstTSBuiltin;
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#define GET_BUILTIN_STR_TABLE
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#include "clang/Basic/BuiltinsBPF.inc"
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#undef GET_BUILTIN_STR_TABLE
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static constexpr Builtin::Info BuiltinInfos[] = {
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#define GET_BUILTIN_INFOS
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#include "clang/Basic/BuiltinsBPF.inc"
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#undef GET_BUILTIN_INFOS
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};
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static_assert(std::size(BuiltinInfos) == NumBuiltins);
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void BPFTargetInfo::getTargetDefines(const LangOptions &Opts,
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MacroBuilder &Builder) const {
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Builder.defineMacro("__bpf__");
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Builder.defineMacro("__BPF__");
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std::string CPU = getTargetOpts().CPU;
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if (CPU == "probe") {
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Builder.defineMacro("__BPF_CPU_VERSION__", "0");
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return;
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}
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Builder.defineMacro("__BPF_FEATURE_ADDR_SPACE_CAST");
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Builder.defineMacro("__BPF_FEATURE_MAY_GOTO");
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Builder.defineMacro("__BPF_FEATURE_ATOMIC_MEM_ORDERING");
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if (CPU.empty())
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CPU = "v3";
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if (CPU == "generic" || CPU == "v1") {
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Builder.defineMacro("__BPF_CPU_VERSION__", "1");
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return;
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}
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std::string CpuVerNumStr = CPU.substr(1);
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Builder.defineMacro("__BPF_CPU_VERSION__", CpuVerNumStr);
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int CpuVerNum = std::stoi(CpuVerNumStr);
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if (CpuVerNum >= 2)
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Builder.defineMacro("__BPF_FEATURE_JMP_EXT");
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if (CpuVerNum >= 3) {
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Builder.defineMacro("__BPF_FEATURE_JMP32");
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Builder.defineMacro("__BPF_FEATURE_ALU32");
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}
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if (CpuVerNum >= 4) {
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Builder.defineMacro("__BPF_FEATURE_LDSX");
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Builder.defineMacro("__BPF_FEATURE_MOVSX");
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Builder.defineMacro("__BPF_FEATURE_BSWAP");
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Builder.defineMacro("__BPF_FEATURE_SDIV_SMOD");
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Builder.defineMacro("__BPF_FEATURE_GOTOL");
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Builder.defineMacro("__BPF_FEATURE_ST");
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Builder.defineMacro("__BPF_FEATURE_LOAD_ACQ_STORE_REL");
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}
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}
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static constexpr llvm::StringLiteral ValidCPUNames[] = {"generic", "v1", "v2",
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"v3", "v4", "probe"};
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bool BPFTargetInfo::isValidCPUName(StringRef Name) const {
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return llvm::is_contained(ValidCPUNames, Name);
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}
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void BPFTargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const {
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Values.append(std::begin(ValidCPUNames), std::end(ValidCPUNames));
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}
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llvm::SmallVector<Builtin::InfosShard>
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BPFTargetInfo::getTargetBuiltins() const {
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return {{&BuiltinStrings, BuiltinInfos}};
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}
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bool BPFTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
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DiagnosticsEngine &Diags) {
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for (const auto &Feature : Features) {
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if (Feature == "+alu32") {
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HasAlu32 = true;
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}
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}
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return true;
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}
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