69e75ae695
This fixes what I consider to be an API flaw I've tripped over multiple times. The point this is constructed isn't well defined, so depending on where this is first called, you can conclude different information based on the MachineFunction. For example, the AMDGPU implementation inspected the MachineFrameInfo on construction for the stack objects and if the frame has calls. This kind of worked in SelectionDAG which visited all allocas up front, but broke in GlobalISel which hasn't visited any of the IR when arguments are lowered. I've run into similar problems before with the MIR parser and trying to make use of other MachineFunction fields, so I think it's best to just categorically disallow dependency on the MachineFunction state in the constructor and to always construct this at the same time as the MachineFunction itself. A missing feature I still could use is a way to access an custom analysis pass on the IR here.
91 lines
3.1 KiB
C++
91 lines
3.1 KiB
C++
//===-- SparcTargetMachine.h - Define TargetMachine for Sparc ---*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file declares the Sparc specific subclass of TargetMachine.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_SPARC_SPARCTARGETMACHINE_H
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#define LLVM_LIB_TARGET_SPARC_SPARCTARGETMACHINE_H
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#include "SparcInstrInfo.h"
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#include "SparcSubtarget.h"
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#include "llvm/Target/TargetMachine.h"
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#include <optional>
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namespace llvm {
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class SparcTargetMachine : public LLVMTargetMachine {
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std::unique_ptr<TargetLoweringObjectFile> TLOF;
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SparcSubtarget Subtarget;
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bool is64Bit;
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mutable StringMap<std::unique_ptr<SparcSubtarget>> SubtargetMap;
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public:
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SparcTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
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StringRef FS, const TargetOptions &Options,
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std::optional<Reloc::Model> RM,
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std::optional<CodeModel::Model> CM, CodeGenOpt::Level OL,
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bool JIT, bool is64bit);
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~SparcTargetMachine() override;
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const SparcSubtarget *getSubtargetImpl() const { return &Subtarget; }
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const SparcSubtarget *getSubtargetImpl(const Function &) const override;
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// Pass Pipeline Configuration
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TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
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TargetLoweringObjectFile *getObjFileLowering() const override {
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return TLOF.get();
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}
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MachineFunctionInfo *
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createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F,
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const TargetSubtargetInfo *STI) const override;
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};
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/// Sparc 32-bit target machine
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///
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class SparcV8TargetMachine : public SparcTargetMachine {
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virtual void anchor();
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public:
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SparcV8TargetMachine(const Target &T, const Triple &TT, StringRef CPU,
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StringRef FS, const TargetOptions &Options,
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std::optional<Reloc::Model> RM,
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std::optional<CodeModel::Model> CM, CodeGenOpt::Level OL,
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bool JIT);
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};
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/// Sparc 64-bit target machine
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///
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class SparcV9TargetMachine : public SparcTargetMachine {
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virtual void anchor();
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public:
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SparcV9TargetMachine(const Target &T, const Triple &TT, StringRef CPU,
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StringRef FS, const TargetOptions &Options,
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std::optional<Reloc::Model> RM,
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std::optional<CodeModel::Model> CM, CodeGenOpt::Level OL,
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bool JIT);
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};
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class SparcelTargetMachine : public SparcTargetMachine {
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virtual void anchor();
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public:
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SparcelTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
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StringRef FS, const TargetOptions &Options,
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std::optional<Reloc::Model> RM,
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std::optional<CodeModel::Model> CM, CodeGenOpt::Level OL,
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bool JIT);
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};
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} // end namespace llvm
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#endif
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