d198c75e5a
This adds the missing handling for defs for target index operands, as is already done for registers. There are two kinds of target indices: local indices and stack operands. - Locals are something similar to registers in Wasm-land. For local indices, we can check for local-defining instructions (`local.set` or `local.tee`). - Wasm is a stack machine, so we have values in certain Wasm value stack location, which change when Wasm instructions produce or consume values. So basically any value-producing instrucion, i.e., instruction with defs, can change values in the Wasm stack. But I think we don't need to worry about this here, because `WebAssemblyDebugFixup`, which runs right before this analysis, makes sure to insert terminating `DBG_VALUE $noreg` instructions whenever a stack value gets popped. After `WebAssemblyDebugFixup`, there shouldn't be any `DBG_VALUE`s for stack operands that don't have a terminating `DBG_VALUE $noreg` within the same BB. So this CL only works on `DBG_VALUE`s for locals. When we encounter a `local.set` or `local.tee` instructions, we delete `DBG_VALUE`s for those target index locations from the open range set, so they will not be availble in `OutLocs`. For example, ``` bb.0: successors: %bb.1 DBG_VALUE target-index(wasm-local) + 2, $noreg, "var", ... ... local.set 2 ... bb.1: ; predecessors: %bb.0 ; We shouldn't add `DBG_VALUE target (wasm-local) + 2 here because ; it was killed by 'local.set' in bb.0 ``` After disabling register coalescing at -O1, the average PC ranges covered for Emscripten core benchmarks is currently 20.6% in the LLVM tot. After applying D138943 and this CL, the coverage goes up to 57%. This also enables LiveDebugValues analysis in the Wasm pipeline by default. Reviewed By: dschuff, jmorse Differential Revision: https://reviews.llvm.org/D140373
80 lines
2.8 KiB
C++
80 lines
2.8 KiB
C++
//=- WebAssemblyInstrInfo.h - WebAssembly Instruction Information -*- C++ -*-=//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// This file contains the WebAssembly implementation of the
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/// TargetInstrInfo class.
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///
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_WEBASSEMBLY_WEBASSEMBLYINSTRINFO_H
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#define LLVM_LIB_TARGET_WEBASSEMBLY_WEBASSEMBLYINSTRINFO_H
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#include "WebAssemblyRegisterInfo.h"
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#define GET_INSTRINFO_HEADER
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#include "WebAssemblyGenInstrInfo.inc"
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#define GET_INSTRINFO_OPERAND_ENUM
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#include "WebAssemblyGenInstrInfo.inc"
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namespace llvm {
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namespace WebAssembly {
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int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIndex);
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}
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class WebAssemblySubtarget;
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class WebAssemblyInstrInfo final : public WebAssemblyGenInstrInfo {
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const WebAssemblyRegisterInfo RI;
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public:
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explicit WebAssemblyInstrInfo(const WebAssemblySubtarget &STI);
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const WebAssemblyRegisterInfo &getRegisterInfo() const { return RI; }
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bool isReallyTriviallyReMaterializable(const MachineInstr &MI) const override;
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void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
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const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
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bool KillSrc) const override;
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MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
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unsigned OpIdx1,
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unsigned OpIdx2) const override;
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bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify = false) const override;
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unsigned removeBranch(MachineBasicBlock &MBB,
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int *BytesRemoved = nullptr) const override;
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unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
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const DebugLoc &DL,
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int *BytesAdded = nullptr) const override;
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bool
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reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
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ArrayRef<std::pair<int, const char *>>
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getSerializableTargetIndices() const override;
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const MachineOperand &getCalleeOperand(const MachineInstr &MI) const override;
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bool isExplicitTargetIndexDef(const MachineInstr &MI, int &Index,
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int64_t &Offset) const override;
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};
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} // end namespace llvm
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#endif
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