Craig Topper ea87cf2acd [TargetLowering][RISCV] Don't transform (seteq/ne (sext_inreg X, VT), C1) -> (seteq/ne (zext_inreg X, VT), C1) if the sext_inreg is cheaper ...

RISCV has to use 2 shifts for (i64 (zext_inreg X, i32)), but we
can use addiw rd, rs1, x0 for sext_inreg. We already understood this
when type legalizing i32 seteq/ne on rv64. But this transform in
SimplifySetCC would sometimes undo it.

Reviewed By: luismarques

Differential Revision: https://reviews.llvm.org/D95289

2021-01-25 16:37:21 -08:00

..

CMakeLists.txt

llvmbuildectomy - replace llvm-build by plain cmake

2020-11-13 10:35:24 +01:00

DAGCombiner.cpp

[SelectionDAG] Support scalable-vector splats in more cases

2021-01-25 10:58:15 +00:00

FastISel.cpp

Introduce llvm.noalias.decl intrinsic

2021-01-16 09:20:45 +01:00

FunctionLoweringInfo.cpp

[Analysis,CodeGen] Make use of KnownBits::makeConstant. NFC.

2021-01-14 14:02:43 +00:00

InstrEmitter.cpp

[CSSPGO] Pseudo probes for function calls.

2020-12-02 13:45:20 -08:00

InstrEmitter.h

[CodeGen] Forward-declare TargetMachine (NFC)

2021-01-24 12:18:54 -08:00

LegalizeDAG.cpp

[llvm] Use the default value of drop_begin (NFC)

2021-01-18 10:16:36 -08:00

LegalizeFloatTypes.cpp

[Legalizer] Promote result type in expanding FP_TO_XINT

2021-01-18 11:56:11 +08:00

LegalizeIntegerTypes.cpp

Add intrinsics for saturating float to int casts

2020-12-18 11:09:41 +01:00

LegalizeTypes.cpp

[llvm] Use pop_back_val (NFC)

2021-01-24 12:18:57 -08:00

LegalizeTypes.h

Add intrinsics for saturating float to int casts

2020-12-18 11:09:41 +01:00

LegalizeTypesGeneric.cpp

[CodeGen] Refactor getMemBasePlusOffset & getObjectPtrOffset to accept a TypeSize

2020-08-11 12:17:10 +01:00

LegalizeVectorOps.cpp

Add intrinsics for saturating float to int casts

2020-12-18 11:09:41 +01:00

LegalizeVectorTypes.cpp

[LegalizeType] When LegalizeType procedure widens a masked_gather, set MemoryType's EltNum equal to Result's EltNum

2020-12-22 13:27:38 +08:00

ResourcePriorityQueue.cpp

ResourcePriorityQueue.h - reduce unnecessary includes to forward declarations. NFC.

2020-05-26 19:22:14 +01:00

ScheduleDAGFast.cpp

[DebugInstrRef] Create DBG_INSTR_REFs in SelectionDAG

2020-10-14 14:24:08 +01:00

ScheduleDAGRRList.cpp

Revert "[NFC][ScheduleDAG] Remove unused EntrySU SUnit"

2020-09-21 13:33:05 +02:00

ScheduleDAGSDNodes.cpp

[CodeGen] Construct SmallVector with iterator ranges (NFC)

2020-12-31 09:39:11 -08:00

ScheduleDAGSDNodes.h

DAG: Use Register

2020-04-08 13:44:31 -04:00

ScheduleDAGVLIW.cpp

Revert "[NFC][ScheduleDAG] Remove unused EntrySU SUnit"

2020-09-21 13:33:05 +02:00

SDNodeDbgValue.h

…

SelectionDAG.cpp

[SelectionDAG] Support scalable-vector splats in more cases

2021-01-25 10:58:15 +00:00

SelectionDAGAddressAnalysis.cpp

[SelectionDAG] Avoid aliasing analysis if the object size is unknown.

2020-11-25 06:13:37 +08:00

SelectionDAGBuilder.cpp

[XRay] Make __xray_customevent support non-Linux

2021-01-25 00:48:21 -08:00

SelectionDAGBuilder.h

[VP] Build VP SDNodes

2020-12-09 11:36:51 +01:00

SelectionDAGDumper.cpp

Add intrinsics for saturating float to int casts

2020-12-18 11:09:41 +01:00

SelectionDAGISel.cpp

[SelectionDAG] Extend immAll(Ones|Zeros)V to handle ISD::SPLAT_VECTOR

2021-01-09 17:05:31 +00:00

SelectionDAGPrinter.cpp

Utility to dump .dot representation of SelectionDAG without firing viewer

2020-06-04 11:51:48 +05:30

SelectionDAGTargetInfo.cpp

…

StatepointLowering.cpp

[Statepoint Lowering] Add an option to allow use gc values in regs for landing pad

2021-01-13 11:39:34 +07:00

StatepointLowering.h

[Statepoint] Consolidate relocation type tracking [NFC]

2020-07-29 11:45:31 -07:00

TargetLowering.cpp

[TargetLowering][RISCV] Don't transform (seteq/ne (sext_inreg X, VT), C1) -> (seteq/ne (zext_inreg X, VT), C1) if the sext_inreg is cheaper

2021-01-25 16:37:21 -08:00