David Sherwood 7c164a9225 [SVE] Fix some logical arithmetic tests
There were some right-shift tests in

  CodeGen/AArch64/sve-int-arith-imm.ll

that were being folded away because we were shifting all the bits
out to the right. I've updated the tests to ensure this doesn't
happen.
2021-01-26 11:06:09 +00:00
..
2020-12-08 11:54:39 +00:00
2019-06-17 09:13:29 +00:00
2019-10-08 13:23:57 +00:00
2019-07-17 19:24:02 +00:00
2019-08-15 10:12:26 +00:00
2020-02-03 11:01:05 +01:00
2019-12-05 18:10:06 +00:00
2021-01-13 10:57:49 +00:00
2019-07-17 19:24:02 +00:00
2020-12-08 10:28:26 +00:00

++ SVE CodeGen Warnings ++

When the WARN check lines fail in the SVE codegen tests it most likely means you
have introduced a warning due to:
1. Adding an invalid call to VectorType::getNumElements() or EVT::getVectorNumElements()
   when the type is a scalable vector.
2. Relying upon an implicit cast conversion from TypeSize to uint64_t.

For generic code, please modify your code to work with ElementCount and TypeSize directly.
For target-specific code that only deals with fixed-width vectors, use the fixed-size interfaces.
Please refer to the code where those functions live for more details.