Matt Arsenault db0bac0ef2

AMDGPU: Form v_med_f32 from minimumnum/maximumnum immediate pattern (#141048) ...

This makes little difference in the final output, as we manage to form this
after these are lowered to the _ieee operations. This does result in fewer steps
in the DAG, and helps prepare for changing the handling of minnum/maxnum.

2025-05-22 21:04:47 +02:00

..

AArch64

[GlobalISel] Add a update_givaluetracking_test_checks.py script (#140296)

2025-05-22 09:06:37 +01:00

AMDGPU

AMDGPU: Form v_med_f32 from minimumnum/maximumnum immediate pattern (#141048)

2025-05-22 21:04:47 +02:00

ARC

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ARM

[BranchFolding] Fix assertion failure in HoistCommonCodeInSuccs (#141028)

2025-05-22 13:21:26 +01:00

AVR

[LangRef] Comment on validity of volatile ops on null (#139803)

2025-05-22 15:12:34 +02:00

BPF

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CSKY

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DirectX

[HLSL] Move FNeg legalization to the DXILLegalization pass (#140942)

2025-05-22 10:43:00 -06:00

Generic

[LLVM][VecLib] Refactor LIBMVEC integration to be target neutral. (#138262)

2025-05-07 11:05:25 +01:00

Hexagon

Hexagon: sfmax/sfmin instructions are IEEE754-2019 (#139056)

2025-05-14 11:55:11 +08:00

Inputs

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Lanai

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LoongArch

[LoongArch] Prevent R0/R1 allocation for rj operand of [G]CSRXCHG (#140862)

2025-05-22 18:49:27 +08:00

M68k

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Mips

[COFF][Mips] Set PrivateGlobalPrefix to .L (#140033)

2025-05-16 11:22:44 +08:00

MIR

[NVPTX] Remove Float register classes (#140487)

2025-05-21 11:33:57 -07:00

MLRegAlloc

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MSP430

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NVPTX

Revert "[NVPTX] Unify and extend barrier{.cta} intrinsic support (#140615)"

2025-05-22 17:28:43 +00:00

PowerPC

Fix typo "redudant"

2025-05-22 15:42:22 +01:00

RISCV

[RISCV] add Double Trap extension requires Zicsr (#141016)

2025-05-23 00:27:04 +08:00

SPARC

[SPARC] Use op-then-neg instructions when we have VIS3 (#138603)

2025-05-06 05:36:29 +07:00

SPIRV

[SPIR-V] Support SPV_INTEL_int4 extension (#141031)

2025-05-22 11:56:54 -07:00

SystemZ

[MCP] Disable BackwardCopyPropagateBlock for copies with implicit registers. (#137687)

2025-05-08 16:27:08 -07:00

Thumb

[MC][AArch64][ARM][X86] Push target-dependent assembler flags into targets (#139844)

2025-05-18 20:09:43 +01:00

Thumb2

[ARM] Remove kill flags in ReplaceConstByVPNOTs. (#140082)

2025-05-22 08:24:01 +01:00

VE

Reland [SelectionDAG] Folding ZERO-EXTEND/SIGN_EXTEND poison to Poison value in getNode (#136701)

2025-04-22 17:36:41 -04:00

WebAssembly

[WebAssembly] Fix trunc in FastISel (#138479)

2025-05-06 14:16:35 -07:00

WinCFGuard

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WinEH

[WinEH] Fix asm in catchpad being turned into unreachable (#138392)

2025-05-08 21:46:51 +02:00

X86

[X86] lowerV4F64Shuffle - prefer BLEND before UNPCK shuffle matching (#141073)

2025-05-22 16:51:00 +01:00

XCore

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Xtensa

[Xtensa] Implement Xtensa Mul and Div Options. (#132157)

2025-04-18 20:22:03 +03:00