shylie/llvm-project

History

Ravil Dorozhinskii 760c4292c0

[MLIR][AMDGPU] Added l2-prefetch op to AMDGPU (#188457 )

This PR adds `global_prefetch` op to prefetch a cache line to high-level
caches using the aligned address of the source `memref` and an offset
provided by the indices of the element containing the cache line. This
provides temporal hints (e.g., regular or high-priority). Note that
out-of-bounds access is allowed in speculative mode. Ensure the source
`memref` is in address space `1`.

---------

Co-authored-by: Krzysztof Drewniak <Krzysztof.Drewniak@amd.com>

2026-03-27 16:05:30 +01:00

..

benchmark/python

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[mlir-python] Fix duplicate EnumAttr builder registration across dialects. (#187191 )

2026-03-19 21:02:23 -07:00

[MLIR][Python][Docs] Fix example of Python-defined dialects (#188174 )

2026-03-24 19:50:49 +08:00

[MLIR] Add missing dialects to C API (#82190 )

2026-01-07 12:51:33 -08:00

[MLIR][AMDGPU] Added l2-prefetch op to AMDGPU (#188457 )

2026-03-27 16:05:30 +01:00

[MLIR][AMDGPU] Added l2-prefetch op to AMDGPU (#188457 )

2026-03-27 16:05:30 +01:00

[MLIR] [Python] More improvements to type annotations (#188468 )

2026-03-25 14:18:29 +00:00

[MLIR][AMDGPU] Added l2-prefetch op to AMDGPU (#188457 )

2026-03-27 16:05:30 +01:00

[mlir][spirv] Add Gather/Scatter/Resize ops in TOSA Ext Inst Set (#188497 )

2026-03-27 15:13:53 +01:00

[mlir] Add Repeated<T> constructors for TypeRange and ValueRange (#186923 )

2026-03-26 07:20:12 -04:00

[mlir] Fix generate-test-checks.py: don't put attr refs in CHECK-LABEL (#188985 )

2026-03-27 14:59:42 +01:00

.clang-format

Enforce Unix line endings for Clang/LLVM/MLIR projects (#161460 )

2025-10-02 06:09:12 -07:00

.clang-tidy

[MLIR][NFC] Ignore clang-tidy modernize-use-using check in C code (#180326 )

2026-02-09 13:24:08 +08:00

CMakeLists.txt

[mlir] Replace MLIR_ENABLE_ROCM_CONVERSIONS with LLVM_HAS_AMDGPU_TARGET (#182652 )

2026-03-13 22:03:05 +00:00

LICENSE.TXT

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Maintainers.md

[mlir][x86] Move AMX dialect into X86 dialect (#183717 )

2026-03-02 11:47:30 +01:00

README.md

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README.md

Multi-Level Intermediate Representation

See https://mlir.llvm.org/ for more information.