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llvm-project/llvm/test/CodeGen
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Artem Belevich dc90f42ea7 Coalesce 16-bit FP types to use integer register classes. 
i16/f16/bf16 will use the same .b16 registers and
i32/v2f16 and v2bf16 will share .b32 registers.

The changes are mostly mechanical, intended to remove unnecessary register
classes which tend to produce redundant register moves.

Differential Revision: https://reviews.llvm.org/D151601

v2f16 regtype conversion to i32
2023-06-05 12:21:52 -07:00
..
AArch64
[AArch64][SVE] Predicated mla/mls patterns
2023-06-05 10:08:57 +01:00
AMDGPU
[AMDGPU] Add intrinsic for converting global pointers to resources
2023-06-05 17:07:59 +00:00
ARC
[NFC][Py Reformat] Reformat lit.local.cfg python files in llvm
2023-05-17 17:03:15 +02:00
ARM
Revert "[DAGCombine] Make sure combined nodes are added back to the worklist in topological order."
2023-06-05 10:55:58 -04:00
AVR
[AVR][NFC][test] Suppement a test of the pseudo instruction RORBRd
2023-06-04 23:19:21 +08:00
BPF
[NFC][Py Reformat] Reformat lit.local.cfg python files in llvm
2023-05-17 17:03:15 +02:00
CSKY
[NFC][Py Reformat] Reformat lit.local.cfg python files in llvm
2023-05-17 17:03:15 +02:00
DirectX
[NFC][Py Reformat] Reformat lit.local.cfg python files in llvm
2023-05-17 17:03:15 +02:00
Generic
LangRef: Add "dynamic" option to "denormal-fp-math"
2023-04-29 08:44:59 -04:00
Hexagon
Revert "[DAGCombine] Make sure combined nodes are added back to the worklist in topological order."
2023-06-05 10:55:58 -04:00
Inputs
[IR] Make stack protector symbol dso_local according to -f[no-]direct-access-external-data
2023-05-23 09:49:57 -07:00
Lanai
[NFC][Py Reformat] Reformat lit.local.cfg python files in llvm
2023-05-17 17:03:15 +02:00
LoongArch
[KnownBits] Return zero instead of unknown for always poison shifts
2023-05-23 14:41:22 +02:00
M68k
[m68k] Add TLS Support
2023-06-03 19:09:47 +08:00
Mips
[NFC][Py Reformat] Reformat lit.local.cfg python files in llvm
2023-05-17 17:03:15 +02:00
MIR
[AMDGPU] Use resource base for buffer instruction MachineMemOperands
2023-06-05 17:06:57 +00:00
MLRegalloc
[NFC][Py Reformat] Reformat python files in llvm
2023-05-17 10:48:52 +02:00
MSP430
[NFC][Py Reformat] Reformat lit.local.cfg python files in llvm
2023-05-17 17:03:15 +02:00
NVPTX
Coalesce 16-bit FP types to use integer register classes.
2023-06-05 12:21:52 -07:00
PowerPC
Revert "[DAGCombine] Make sure combined nodes are added back to the worklist in topological order."
2023-06-05 10:55:58 -04:00
RISCV
Revert "[DAGCombine] Make sure combined nodes are added back to the worklist in topological order."
2023-06-05 10:55:58 -04:00
SPARC
[NFC][Py Reformat] Reformat lit.local.cfg python files in llvm
2023-05-17 17:03:15 +02:00
SPIRV
[NFC][Py Reformat] Reformat lit.local.cfg python files in llvm
2023-05-17 17:03:15 +02:00
SystemZ
Revert "[DAGCombine] Make sure combined nodes are added back to the worklist in topological order."
2023-06-05 10:55:58 -04:00
Thumb
[IR] Make stack protector symbol dso_local according to -f[no-]direct-access-external-data
2023-05-23 09:49:57 -07:00
Thumb2
Revert "[DAGCombine] Make sure combined nodes are added back to the worklist in topological order."
2023-06-05 10:55:58 -04:00
VE
[LegalizeTypes][ARM][AArch6][RISCV][VE][WebAssembly] Add special case for smin(X, -1) and smax(X, 0) to ExpandIntRes_MINMAX.
2023-05-23 09:19:55 -07:00
WebAssembly
[LegalizeTypes][ARM][AArch6][RISCV][VE][WebAssembly] Add special case for smin(X, -1) and smax(X, 0) to ExpandIntRes_MINMAX.
2023-05-23 09:19:55 -07:00
WinCFGuard
[NFC][Py Reformat] Reformat lit.local.cfg python files in llvm
2023-05-17 17:03:15 +02:00
WinEH
[NFC][Py Reformat] Reformat lit.local.cfg python files in llvm
2023-05-17 17:03:15 +02:00
X86
Revert "[DAGCombine] Make sure combined nodes are added back to the worklist in topological order."
2023-06-05 10:55:58 -04:00
XCore
[XCore] Use backwards scavenging in frame index elimination
2023-05-18 09:58:53 +01:00