dcb834843e
This is only used by CodeGen. Moving it out of AMDGPUBaseInfo simplifies future changes to make some of it depend on the subtarget. Differential Revision: https://reviews.llvm.org/D144650
122 lines
4.6 KiB
C++
122 lines
4.6 KiB
C++
//===-- SIModeRegisterDefaults.h --------------------------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AMDGPU_SIMODEREGISTERDEFAULTS_H
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#define LLVM_LIB_TARGET_AMDGPU_SIMODEREGISTERDEFAULTS_H
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#include "Utils/AMDGPUBaseInfo.h"
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#include "llvm/ADT/FloatingPointMode.h"
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namespace llvm {
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// Track defaults for fields in the MODE register.
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struct SIModeRegisterDefaults {
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/// Floating point opcodes that support exception flag gathering quiet and
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/// propagate signaling NaN inputs per IEEE 754-2008. Min_dx10 and max_dx10
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/// become IEEE 754- 2008 compliant due to signaling NaN propagation and
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/// quieting.
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bool IEEE : 1;
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/// Used by the vector ALU to force DX10-style treatment of NaNs: when set,
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/// clamp NaN to zero; otherwise, pass NaN through.
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bool DX10Clamp : 1;
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/// If this is set, neither input or output denormals are flushed for most f32
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/// instructions.
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DenormalMode FP32Denormals;
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/// If this is set, neither input or output denormals are flushed for both f64
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/// and f16/v2f16 instructions.
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DenormalMode FP64FP16Denormals;
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SIModeRegisterDefaults()
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: IEEE(true), DX10Clamp(true), FP32Denormals(DenormalMode::getIEEE()),
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FP64FP16Denormals(DenormalMode::getIEEE()) {}
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SIModeRegisterDefaults(const Function &F);
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static SIModeRegisterDefaults getDefaultForCallingConv(CallingConv::ID CC) {
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SIModeRegisterDefaults Mode;
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Mode.IEEE = !AMDGPU::isShader(CC);
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return Mode;
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}
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bool operator==(const SIModeRegisterDefaults Other) const {
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return IEEE == Other.IEEE && DX10Clamp == Other.DX10Clamp &&
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FP32Denormals == Other.FP32Denormals &&
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FP64FP16Denormals == Other.FP64FP16Denormals;
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}
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bool allFP32Denormals() const {
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return FP32Denormals == DenormalMode::getIEEE();
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}
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bool allFP64FP16Denormals() const {
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return FP64FP16Denormals == DenormalMode::getIEEE();
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}
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/// Get the encoding value for the FP_DENORM bits of the mode register for the
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/// FP32 denormal mode.
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uint32_t fpDenormModeSPValue() const {
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if (FP32Denormals == DenormalMode::getPreserveSign())
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return FP_DENORM_FLUSH_IN_FLUSH_OUT;
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if (FP32Denormals.Output == DenormalMode::PreserveSign)
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return FP_DENORM_FLUSH_OUT;
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if (FP32Denormals.Input == DenormalMode::PreserveSign)
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return FP_DENORM_FLUSH_IN;
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return FP_DENORM_FLUSH_NONE;
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}
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/// Get the encoding value for the FP_DENORM bits of the mode register for the
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/// FP64/FP16 denormal mode.
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uint32_t fpDenormModeDPValue() const {
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if (FP64FP16Denormals == DenormalMode::getPreserveSign())
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return FP_DENORM_FLUSH_IN_FLUSH_OUT;
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if (FP64FP16Denormals.Output == DenormalMode::PreserveSign)
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return FP_DENORM_FLUSH_OUT;
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if (FP64FP16Denormals.Input == DenormalMode::PreserveSign)
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return FP_DENORM_FLUSH_IN;
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return FP_DENORM_FLUSH_NONE;
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}
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/// Returns true if a flag is compatible if it's enabled in the callee, but
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/// disabled in the caller.
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static bool oneWayCompatible(bool CallerMode, bool CalleeMode) {
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return CallerMode == CalleeMode || (!CallerMode && CalleeMode);
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}
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// FIXME: Inlining should be OK for dx10-clamp, since the caller's mode should
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// be able to override.
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bool isInlineCompatible(SIModeRegisterDefaults CalleeMode) const {
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if (DX10Clamp != CalleeMode.DX10Clamp)
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return false;
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if (IEEE != CalleeMode.IEEE)
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return false;
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// Allow inlining denormals enabled into denormals flushed functions.
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return oneWayCompatible(FP64FP16Denormals.Input !=
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DenormalMode::PreserveSign,
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CalleeMode.FP64FP16Denormals.Input !=
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DenormalMode::PreserveSign) &&
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oneWayCompatible(FP64FP16Denormals.Output !=
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DenormalMode::PreserveSign,
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CalleeMode.FP64FP16Denormals.Output !=
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DenormalMode::PreserveSign) &&
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oneWayCompatible(FP32Denormals.Input != DenormalMode::PreserveSign,
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CalleeMode.FP32Denormals.Input !=
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DenormalMode::PreserveSign) &&
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oneWayCompatible(FP32Denormals.Output != DenormalMode::PreserveSign,
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CalleeMode.FP32Denormals.Output !=
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DenormalMode::PreserveSign);
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}
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};
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} // end namespace llvm
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#endif // LLVM_LIB_TARGET_AMDGPU_SIMODEREGISTERDEFAULTS_H
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