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llvm-project/llvm/lib/Target/AArch64
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David Green dccc69a38d [AArch64] Add extra reverse costs. 
This adds some extra costs for reverse shuffles under AArch64, filling
in the i16/f16/i8 gaps in the cost model.

Differential Revision: https://reviews.llvm.org/D124786
2022-05-06 18:23:36 +01:00
..
AsmParser
[AArch64] validateTargetOperandClass - early out from MCK_MPR case. NFCI.
2022-04-09 10:07:58 +01:00
Disassembler
[Disassember][NFCI] Use strong type for instruction decoder
2022-03-25 18:53:59 -07:00
GISel
AArch64/GlobalISel: Reduce use of getMinClassForRegBank
2022-04-19 21:04:32 -04:00
MCTargetDesc
[MC][AArch64] Enable '+v8a' when nothing specified for MCSubtargetInfo
2022-04-29 04:53:22 +08:00
TargetInfo
Fix shlib builds for all lib/Target/*/TargetInfo libs
2021-10-08 15:21:13 -07:00
Utils
[SVE][CodeGen] Use splice instruction when lowering VECTOR_SPLICE
2022-01-11 11:58:17 +00:00
AArch64.h
[CodeGen] Async unwind - add a pass to fix CFI information
2022-04-11 13:27:26 +01:00
AArch64.td
[AArch64] Support for Ampere1 core
2022-05-03 15:54:02 +01:00
AArch64A53Fix835769.cpp
Fix warnings about variables that are set but only used in debug mode
2022-04-06 10:01:46 +03:00
AArch64A57FPLoadBalancing.cpp
…
AArch64AdvSIMDScalarPass.cpp
[llvm] Use range-based for loops (NFC)
2021-12-11 11:29:12 -08:00
AArch64AsmPrinter.cpp
[AArch64][GlobalISel] CodeGen for Armv8.8/9.3 MOPS
2022-01-31 20:54:41 +00:00
AArch64BranchTargets.cpp
…
AArch64CallingConvention.cpp
…
AArch64CallingConvention.h
…
AArch64CallingConvention.td
AArch64: don't claim to preserve registers used by prologue code
2022-01-10 12:27:04 +00:00
AArch64CleanupLocalDynamicTLSPass.cpp
…
AArch64CollectLOH.cpp
[AArch64][LOH] Don't ignore regmasks in bundles by iterating over instrs.
2022-04-12 10:34:54 -07:00
AArch64Combine.td
[AArch64][GlobalISel] Add undef combines to postlegalizer combiner.
2022-05-05 09:22:08 -07:00
AArch64CompressJumpTables.cpp
…
AArch64CondBrTuning.cpp
[llvm] Use range-based for loops (NFC)
2021-11-28 10:04:54 -08:00
AArch64ConditionalCompares.cpp
[NFC][CodeGen] Rename some functions in MachineInstr.h and remove duplicated comments
2022-03-16 20:25:42 +08:00
AArch64ConditionOptimizer.cpp
…
AArch64DeadRegisterDefinitionsPass.cpp
…
AArch64ExpandImm.cpp
[llvm] Use range-based for loops (NFC)
2021-12-11 11:29:12 -08:00
AArch64ExpandImm.h
…
AArch64ExpandPseudoInsts.cpp
Reland "[llvm][AArch64] Insert "bti j" after call to setjmp"
2022-03-23 11:43:43 +00:00
AArch64FalkorHWPFFix.cpp
[llvm] Use depth_first (NFC)
2021-12-21 22:28:48 -08:00
AArch64FastISel.cpp
Reland "[llvm][AArch64] Insert "bti j" after call to setjmp"
2022-03-23 11:43:43 +00:00
AArch64FrameLowering.cpp
[AArch64][SVE] Restore SP from FP when SVE CSRs and variable sized objects are present
2022-05-04 12:57:03 +00:00
AArch64FrameLowering.h
[AArch64] Async unwind - function epilogues
2022-04-12 16:50:50 +01:00
AArch64GenRegisterBankInfo.def
…
AArch64InstrAtomics.td
AArch64: do not use xzr for ldxp -> stxp dataflow.
2022-02-09 12:29:16 +00:00
AArch64InstrFormats.td
Reland "[COFF, ARM64] Add __break intrinsic"
2022-04-20 13:01:30 -07:00
AArch64InstrGISel.td
…
AArch64InstrInfo.cpp
[AArch64] Emit .cfi_negate_ra_state for PAC-auth instructions.
2022-04-22 13:25:57 +02:00
AArch64InstrInfo.h
[AArch64] Async unwind - function epilogues
2022-04-12 16:50:50 +01:00
AArch64InstrInfo.td
[NFC] Rename Instrinsic to Intrinsic
2022-04-25 18:13:23 +01:00
AArch64ISelDAGToDAG.cpp
[AArch64][SVE] Only fold frame indexes referencing SVE objects into SVE loads/stores
2022-05-03 09:48:13 +00:00
AArch64ISelLowering.cpp
[SVE] Move reg+reg gather/scatter addressing optimisations from lowering into DAG combine.
2022-04-29 17:42:33 +01:00
AArch64ISelLowering.h
[Arch64][SelectionDAG] Add target-specific implementation of srem
2022-04-19 02:49:42 +08:00
AArch64LoadStoreOptimizer.cpp
[AArch64] Async unwind - Adjust unwind info in AArch64LoadStoreOptimizer
2022-04-18 12:09:44 +01:00
AArch64LowerHomogeneousPrologEpilog.cpp
[llvm] Use llvm::is_contained (NFC)
2021-10-14 22:44:09 -07:00
AArch64MachineFunctionInfo.cpp
[AArch64] Async unwind - function epilogues
2022-04-12 16:50:50 +01:00
AArch64MachineFunctionInfo.h
AArch64: Use Register
2022-04-19 21:07:04 -04:00
AArch64MacroFusion.cpp
[AArch64] Split fuse-literals feature
2022-04-11 05:27:11 +00:00
AArch64MacroFusion.h
…
AArch64MCInstLower.cpp
…
AArch64MCInstLower.h
[Target] Remove unused forward declarations (NFC)
2022-01-02 10:20:15 -08:00
AArch64MIPeepholeOpt.cpp
[AArch64] Adds SUBS and ADDS instructions to the MIPeepholeOpt.
2022-02-19 15:35:53 +00:00
AArch64PBQPRegAlloc.cpp
…
AArch64PBQPRegAlloc.h
…
AArch64PerfectShuffle.h
[AArch64] Use PerfectShuffle costs in AArch64TTIImpl::getShuffleCost
2022-04-27 12:09:01 +01:00
AArch64PfmCounters.td
…
AArch64PromoteConstant.cpp
…
AArch64RedundantCopyElimination.cpp
…
AArch64RegisterBanks.td
…
AArch64RegisterInfo.cpp
[AArch64] Async unwind - Fix MTE codegen emitting frame adjustments in a loop
2022-04-15 14:00:23 +01:00
AArch64RegisterInfo.h
…
AArch64RegisterInfo.td
[AArch64][SVE] NFC: Remove unused p0-p7 with element size predicates
2021-08-10 07:56:22 +00:00
AArch64SchedA53.td
[AArch64] Model Cortex-A55 Q register NEON instructions
2021-09-29 16:55:31 +01:00
AArch64SchedA55.td
Partially revert "[SchedModels][CortexA55] Add ASIMD integer instructions"
2022-02-28 10:58:52 +00:00
AArch64SchedA57.td
[AArch64] Rename CPY to DUP. NFC
2022-01-05 20:02:39 +00:00
AArch64SchedA57WriteRes.td
…
AArch64SchedA64FX.td
[AArch64] Rename CPY to DUP. NFC
2022-01-05 20:02:39 +00:00
AArch64SchedAmpere1.td
[AArch64] Support for Ampere1 core
2022-05-03 15:54:02 +01:00
AArch64SchedCyclone.td
[AArch64] Model Cortex-A55 Q register NEON instructions
2021-09-29 16:55:31 +01:00
AArch64SchedExynosM3.td
[AArch64] Rename CPY to DUP. NFC
2022-01-05 20:02:39 +00:00
AArch64SchedExynosM4.td
[AArch64] Rename CPY to DUP. NFC
2022-01-05 20:02:39 +00:00
AArch64SchedExynosM5.td
[AArch64] Rename CPY to DUP. NFC
2022-01-05 20:02:39 +00:00
AArch64SchedFalkor.td
[AArch64] Model Cortex-A55 Q register NEON instructions
2021-09-29 16:55:31 +01:00
AArch64SchedFalkorDetails.td
[AArch64] Rename CPY to DUP. NFC
2022-01-05 20:02:39 +00:00
AArch64SchedKryo.td
[AArch64] Model Cortex-A55 Q register NEON instructions
2021-09-29 16:55:31 +01:00
AArch64SchedKryoDetails.td
…
AArch64SchedPredAmpere.td
[AArch64] Support for Ampere1 core
2022-05-03 15:54:02 +01:00
AArch64SchedPredExynos.td
[AArch64][SchedModels] Handle virtual registers in FP/NEON predicates
2022-02-17 13:41:05 +03:00
AArch64SchedPredicates.td
[AArch64] Support for Ampere1 core
2022-05-03 15:54:02 +01:00
AArch64SchedThunderX2T99.td
[AArch64] Rename CPY to DUP. NFC
2022-01-05 20:02:39 +00:00
AArch64SchedThunderX3T110.td
[AArch64] Rename CPY to DUP. NFC
2022-01-05 20:02:39 +00:00
AArch64SchedThunderX.td
[AArch64] Model Cortex-A55 Q register NEON instructions
2021-09-29 16:55:31 +01:00
AArch64SchedTSV110.td
[AArch64] Model Cortex-A55 Q register NEON instructions
2021-09-29 16:55:31 +01:00
AArch64Schedule.td
[AArch64] Model Cortex-A55 Q register NEON instructions
2021-09-29 16:55:31 +01:00
AArch64SelectionDAGInfo.cpp
[AArch64][SelectionDAG] CodeGen for Armv8.8/9.3 MOPS
2022-01-31 20:56:27 +00:00
AArch64SelectionDAGInfo.h
[AArch64][SelectionDAG] CodeGen for Armv8.8/9.3 MOPS
2022-01-31 20:56:27 +00:00
AArch64SIMDInstrOpt.cpp
[llvm] Use nullptr instead of 0 (NFC)
2021-12-28 08:52:25 -08:00
AArch64SLSHardening.cpp
[NFC][CodeGen] Rename some functions in MachineInstr.h and remove duplicated comments
2022-03-16 20:25:42 +08:00
AArch64SMEInstrInfo.td
[AArch64][SME] Add rdsvl instruction
2022-02-28 23:14:50 +00:00
AArch64SpeculationHardening.cpp
[NFC] Use Register instead of unsigned
2022-01-19 20:17:04 +08:00
AArch64StackTagging.cpp
[NFC] Rename Instrinsic to Intrinsic
2022-04-25 18:13:23 +01:00
AArch64StackTaggingPreRA.cpp
[NFC] Use Register instead of unsigned
2022-01-19 20:17:04 +08:00
AArch64StorePairSuppress.cpp
[AArch64] Disable AArch64StorePairSuppress under optsize
2021-10-04 18:28:15 +01:00
AArch64Subtarget.cpp
[AArch64] Add -aarch64-insert-extract-base-cost
2022-05-05 10:35:45 +00:00
AArch64Subtarget.h
[AArch64] Add -aarch64-insert-extract-base-cost
2022-05-05 10:35:45 +00:00
AArch64SVEInstrInfo.td
[AArch64][SVE] Remove BIC from logical operation DestructiveBinaryComm patterns
2022-04-22 15:07:55 +01:00
AArch64SystemOperands.td
[AArch64] Make PMMIR_EL1 read-only.
2022-04-05 11:09:56 +01:00
AArch64TargetMachine.cpp
[CodeGen] Async unwind - add a pass to fix CFI information
2022-04-11 13:27:26 +01:00
AArch64TargetMachine.h
mark getTargetTransformInfo and getTargetIRAnalysis as const
2022-02-25 14:30:44 -05:00
AArch64TargetObjectFile.cpp
[Target] Remove redundant member initialization (NFC)
2022-01-06 22:01:44 -08:00
AArch64TargetObjectFile.h
[Target] Remove unused forward declarations (NFC)
2022-01-02 10:20:15 -08:00
AArch64TargetTransformInfo.cpp
[AArch64] Add extra reverse costs.
2022-05-06 18:23:36 +01:00
AArch64TargetTransformInfo.h
Recommit "[SLP][TTI] Refactoring of getShuffleCost Args to work like getArithmeticInstrCost"
2022-04-26 14:02:40 -07:00
CMakeLists.txt
Third Recommit "[AArch64] Split bitmask immediate of bitwise AND operation"
2021-10-08 11:28:49 +01:00
SMEInstrFormats.td
[AArch64][SME] Update DUP (predicate) instruction
2021-10-07 08:55:11 +00:00
SVEInstrFormats.td
[AArch64][SVE] Add some logical operation DestructiveBinaryComm patterns
2022-04-22 20:31:00 +08:00
SVEIntrinsicOpts.cpp
[Aarch64] Remove redundant declaration initializeSVEIntrinsicOptsPass (NFC)
2022-01-01 09:14:25 -08:00