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llvm-project/llvm/lib/Target/RISCV
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wangpc 4ff5e8184c [RISCV] Enable MachineOutliner by default under -Oz for RISCV 
Enable default outlining when the function has the minsize attribute.

`addr-label.ll` crashed after enabling this, so a barrier is added before
instruction selection as a workaround.

Reviewed By: luismarques

Differential Revision: https://reviews.llvm.org/D122213
2022-05-06 17:37:45 +08:00
..
AsmParser
[RISCV] Add a encodeLMUL function to RISCVVType. NFC
2022-04-12 13:39:47 -07:00
Disassembler
[Disassember][NFCI] Use strong type for instruction decoder
2022-03-25 18:53:59 -07:00
MCTargetDesc
[RISCV] Improve constant materialization for cases that can use LUI+ADDI instead of LUI+ADDIW.
2022-04-29 08:58:32 -07:00
TargetInfo
Fix shlib builds for all lib/Target/*/TargetInfo libs
2021-10-08 15:21:13 -07:00
CMakeLists.txt
[RISCV] Enable MachineOutliner by default under -Oz for RISCV
2022-05-06 17:37:45 +08:00
RISCV.h
[RISCV] Lower case the first letter of LowerRISCVMachineOperandToMCOperand. NFC
2022-05-01 14:13:55 -07:00
RISCV.td
[RISCV] Remove ExtZvl enum from RISCVSubtarget. NFC
2022-04-11 10:01:17 -07:00
RISCVAsmPrinter.cpp
[RISCV] Lower case the first letter of LowerRISCVMachineOperandToMCOperand. NFC
2022-05-01 14:13:55 -07:00
RISCVCallingConv.td
…
RISCVCallLowering.cpp
…
RISCVCallLowering.h
…
RISCVExpandAtomicPseudoInsts.cpp
[RISCV] Update comments about getInstSizeInBytes hard-coding the number of bytes.
2022-01-28 09:51:49 -08:00
RISCVExpandPseudoInsts.cpp
[RISCV] Update comments about getInstSizeInBytes hard-coding the number of bytes.
2022-01-28 09:51:49 -08:00
RISCVFrameLowering.cpp
[RISCV] Don't getDebugLoc for the end node of MBB iterator
2022-04-30 16:00:20 +08:00
RISCVFrameLowering.h
Revert "[RISCV] Enable shrink wrap by default"
2022-02-12 19:04:12 +01:00
RISCVGatherScatterLowering.cpp
[RISCV] Remove unnecessary cast to i8* when converting gather/scatter to strided load/store.
2022-04-09 20:05:03 -07:00
RISCVInsertVSETVLI.cpp
[riscv] Use X0 for destination of VSETVLI instruction if result unused
2022-05-05 07:39:45 -07:00
RISCVInstrFormats.td
[RISCV] Support mask policy for RVV IR intrinsics.
2022-03-22 01:19:16 -07:00
RISCVInstrFormatsC.td
…
RISCVInstrFormatsV.td
[RISCV] Remove Zvamo Extention
2021-12-20 10:28:39 +08:00
RISCVInstrInfo.cpp
[RISCV] Enable MachineOutliner by default under -Oz for RISCV
2022-05-06 17:37:45 +08:00
RISCVInstrInfo.h
[RISCV] Enable MachineOutliner by default under -Oz for RISCV
2022-05-06 17:37:45 +08:00
RISCVInstrInfo.td
[RISCV] Remove 'frameindex' from list for ComplexPattern. NFC
2022-04-29 17:41:07 -07:00
RISCVInstrInfoA.td
[RISCV] Change GPRMemAtomic to GPRMemZeroOffset for general usage
2022-02-28 14:02:43 +08:00
RISCVInstrInfoC.td
[llvm-tblgen][RISCV] Make llvm-tblgen RISCVCompressInstEmitter to be common infra across different targets
2021-11-18 11:14:27 +08:00
RISCVInstrInfoD.td
[RISCV] Add isCommutable to FADD/FMUL/FMIN/FMAX/FEQ.
2022-05-02 20:21:16 -07:00
RISCVInstrInfoF.td
[RISCV] Add isCommutable to FADD/FMUL/FMIN/FMAX/FEQ.
2022-05-02 20:21:16 -07:00
RISCVInstrInfoM.td
[RISCV] Add isCommutable to ADD/ADDW/MUL/AND/OR/XOR/MIN/MAX/CLMUL
2022-04-25 10:53:41 -07:00
RISCVInstrInfoV.td
[RISCV][RVV] Add Uses = [FRM] and mayRaiseFPException = true to RVV instructions
2022-03-31 01:33:17 -07:00
RISCVInstrInfoVPseudos.td
[RISCV] Fix alias printing for vmnot.m
2022-04-28 08:33:52 -07:00
RISCVInstrInfoVSDPatterns.td
[RISCV][NFC] Refactor patterns for Multiply Add instructions
2022-04-14 08:00:00 +00:00
RISCVInstrInfoVVLPatterns.td
[RISCV][NFC] Use true_mask replace riscv_vmset_vl in defined patterns.
2022-05-05 03:05:52 +00:00
RISCVInstrInfoZb.td
[RISCV][NFC] Update and add missing closed curly bracket comment in RISCVInstrInfoZb.td
2022-04-27 15:08:51 +08:00
RISCVInstrInfoZfh.td
[RISCV] Add isCommutable to FADD/FMUL/FMIN/FMAX/FEQ.
2022-05-02 20:21:16 -07:00
RISCVInstrInfoZk.td
[RISCV] Adjust some comments.
2022-02-01 22:53:54 +08:00
RISCVInstructionSelector.cpp
[Target] Remove redundant member initialization (NFC)
2022-01-06 22:01:44 -08:00
RISCVISelDAGToDAG.cpp
[RISCV] Fix incorrect codegen for masked vmsge{u}.vx with mask agnostic.
2022-05-02 17:57:29 -07:00
RISCVISelDAGToDAG.h
[RISCV][RVV] Select unmasked TU RVV pseudos in a DAG post-process
2022-04-26 20:14:54 -07:00
RISCVISelLowering.cpp
[RISCV] Update isLegalAddressingMode for RVV.
2022-05-03 19:49:11 -07:00
RISCVISelLowering.h
[RISCV] Support VP_SETCC mask operations
2022-04-28 08:52:29 +00:00
RISCVLegalizerInfo.cpp
[globalisel][legalizer] Separate the deprecated LegalizerInfo from the current one
2021-06-01 13:23:48 -07:00
RISCVLegalizerInfo.h
…
RISCVMachineFunctionInfo.cpp
[RISCV] Store/restore RISCVMachineFunctionInfo into MIR YAML file
2022-04-08 11:55:48 +08:00
RISCVMachineFunctionInfo.h
[RISCV] Store/restore RISCVMachineFunctionInfo into MIR YAML file
2022-04-08 11:55:48 +08:00
RISCVMCInstLower.cpp
[RISCV] Lower case the first letter of LowerRISCVMachineOperandToMCOperand. NFC
2022-05-01 14:13:55 -07:00
RISCVMergeBaseOffset.cpp
[NFC][CodeGen] Rename some functions in MachineInstr.h and remove duplicated comments
2022-03-16 20:25:42 +08:00
RISCVRedundantCopyElimination.cpp
[RISCV] Implement a basic version of AArch64RedundantCopyElimination pass.
2022-02-04 10:43:46 -08:00
RISCVRegisterBankInfo.cpp
[Target] Apply clang-tidy fixes for readability-redundant-member-init (NFC)
2022-03-27 22:22:37 -07:00
RISCVRegisterBankInfo.h
[nfc][codegen] Move RegisterBank[Info].h under CodeGen
2022-03-01 21:53:25 -08:00
RISCVRegisterBanks.td
…
RISCVRegisterInfo.cpp
Drop some more global std::maps. NFCI.
2022-03-06 13:28:29 +01:00
RISCVRegisterInfo.h
[RISCV] Set CostPerUse to 1 iff RVC is enabled
2022-01-21 14:44:26 +08:00
RISCVRegisterInfo.td
[RISCV] add the MC layer support of Zfinx extension
2022-03-02 14:25:19 +08:00
RISCVSchedRocket.td
[RISCV] Add schedule class for Zbp extension and Zbr extension
2022-03-01 07:35:59 +00:00
RISCVSchedSiFive7.td
[RISCV] Add schedule class for Zbp extension and Zbr extension
2022-03-01 07:35:59 +00:00
RISCVSchedule.td
[RISCV] Add scheduling resources for V
2021-08-03 15:47:51 -05:00
RISCVScheduleB.td
[RISCV] Add schedule class for Zbp extension and Zbr extension
2022-03-01 07:35:59 +00:00
RISCVScheduleV.td
[RISCV] Add scheduling resources for V
2021-08-03 15:47:51 -05:00
RISCVSExtWRemoval.cpp
[RISCV] transform MI to W variant to remove sext.w
2022-04-22 10:59:26 -07:00
RISCVSubtarget.cpp
[RISCV] Add a special case to treat riscv-v-vector-bits-min=-1 as meaning use Zvl*b value.
2022-05-04 14:26:45 -07:00
RISCVSubtarget.h
[RISCV] Remove riscv-v-fixed-length-vector-elen-max command line option.
2022-04-11 10:14:48 -07:00
RISCVSystemOperands.td
[RISCV] Initially support the K-extension instructions on the LLVM MC layer
2022-01-24 14:45:35 +08:00
RISCVTargetMachine.cpp
[RISCV] Enable MachineOutliner by default under -Oz for RISCV
2022-05-06 17:37:45 +08:00
RISCVTargetMachine.h
[RISCV] Store/restore RISCVMachineFunctionInfo into MIR YAML file
2022-04-08 11:55:48 +08:00
RISCVTargetObjectFile.cpp
…
RISCVTargetObjectFile.h
…
RISCVTargetTransformInfo.cpp
[RISCV] Add cost model for SK_Broadcast
2022-04-29 13:28:02 +08:00
RISCVTargetTransformInfo.h
Recommit "[SLP][TTI] Refactoring of getShuffleCost Args to work like getArithmeticInstrCost"
2022-04-26 14:02:40 -07:00