213 lines
8.0 KiB
TableGen
213 lines
8.0 KiB
TableGen
//===-- PPCInstrFuture.td - Future Instruction Set --------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the instructions introduced for the Future CPU.
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//
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//===----------------------------------------------------------------------===//
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class XOForm_RTAB5_L1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
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string asmstr, list<dag> pattern>
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: I<opcode, OOL, IOL, asmstr, NoItinerary> {
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bits<5> RT;
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bits<5> RA;
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bits<5> RB;
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bit L;
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let Pattern = pattern;
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bit RC = 0; // set by isRecordForm
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let Inst{6...10} = RT;
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let Inst{11...15} = RA;
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let Inst{16...20} = RB;
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let Inst{21} = L;
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let Inst{22...30} = xo;
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let Inst{31} = RC;
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}
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multiclass XOForm_RTAB5_L1r<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
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string asmbase, string asmstr, list<dag> pattern> {
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let BaseName = asmbase in {
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def NAME : XOForm_RTAB5_L1<opcode, xo, OOL, IOL,
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!strconcat(asmbase, !strconcat(" ", asmstr)),
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pattern>,
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RecFormRel;
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let Defs = [CR0] in def _rec
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: XOForm_RTAB5_L1<opcode, xo, OOL, IOL,
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!strconcat(asmbase, !strconcat(". ", asmstr)), []>,
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isRecordForm, RecFormRel;
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}
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}
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class VXForm_VRTB5<bits<11> xo, bits<5> R, dag OOL, dag IOL, string asmstr,
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list<dag> pattern> : I<4, OOL, IOL, asmstr, NoItinerary> {
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bits<5> VRT;
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bits<5> VRB;
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let Pattern = pattern;
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let Inst{6...10} = VRT;
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let Inst{11...15} = R;
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let Inst{16...20} = VRB;
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let Inst{21...31} = xo;
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}
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class VXForm_VRTB5_UIM2<bits<11> xo, bits<3> R, dag OOL, dag IOL, string asmstr,
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list<dag> pattern>
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: I<4, OOL, IOL, asmstr, NoItinerary> {
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bits<5> VRT;
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bits<5> VRB;
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bits<2> UIM;
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let Pattern = pattern;
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let Inst{6...10} = VRT;
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let Inst{11...13} = R;
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let Inst{14...15} = UIM;
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let Inst{16...20} = VRB;
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let Inst{21...31} = xo;
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}
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class VXForm_VRTB5_UIM1<bits<11> xo, bits<4> R, dag OOL, dag IOL, string asmstr,
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list<dag> pattern>
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: I<4, OOL, IOL, asmstr, NoItinerary> {
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bits<5> VRT;
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bits<5> VRB;
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bits<1> UIM;
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let Pattern = pattern;
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let Inst{6...10} = VRT;
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let Inst{11...14} = R;
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let Inst{15} = UIM;
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let Inst{16...20} = VRB;
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let Inst{21...31} = xo;
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}
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class VXForm_VRTB5_UIM3<bits<11> xo, bits<2> R, dag OOL, dag IOL, string asmstr,
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list<dag> pattern>
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: I<4, OOL, IOL, asmstr, NoItinerary> {
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bits<5> VRT;
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bits<5> VRB;
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bits<3> UIM;
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let Pattern = pattern;
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let Inst{6...10} = VRT;
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let Inst{11...12} = R;
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let Inst{13...15} = UIM;
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let Inst{16...20} = VRB;
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let Inst{21...31} = xo;
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}
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class VXForm_VRTAB5<bits<11> xo, dag OOL, dag IOL, string asmstr,
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list<dag> pattern> : I<4, OOL, IOL, asmstr, NoItinerary> {
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bits<5> VRT;
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bits<5> VRA;
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bits<5> VRB;
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let Pattern = pattern;
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let Inst{6...10} = VRT;
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let Inst{11...15} = VRA;
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let Inst{16...20} = VRB;
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let Inst{21...31} = xo;
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}
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let Predicates = [IsISAFuture] in {
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defm SUBFUS : XOForm_RTAB5_L1r<31, 72, (outs g8rc:$RT),
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(ins g8rc:$RA, g8rc:$RB, u1imm:$L), "subfus",
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"$RT, $L, $RA, $RB", []>;
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}
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let Predicates = [HasVSX, IsISAFuture] in {
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let mayLoad = 1 in {
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def LXVRL : XX1Form_memOp<31, 525, (outs vsrc:$XT),
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(ins (memr $RA):$addr, g8rc:$RB),
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"lxvrl $XT, $addr, $RB", IIC_LdStLoad, []>;
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def LXVRLL : XX1Form_memOp<31, 557, (outs vsrc:$XT),
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(ins (memr $RA):$addr, g8rc:$RB),
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"lxvrll $XT, $addr, $RB", IIC_LdStLoad, []>;
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def LXVPRL : XForm_XTp5_XAB5<31, 589, (outs vsrprc:$XTp),
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(ins (memr $RA):$addr, g8rc:$RB),
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"lxvprl $XTp, $addr, $RB", IIC_LdStLFD, []>;
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def LXVPRLL : XForm_XTp5_XAB5<31, 621, (outs vsrprc:$XTp),
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(ins (memr $RA):$addr, g8rc:$RB),
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"lxvprll $XTp, $addr, $RB", IIC_LdStLFD, []>;
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}
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let mayStore = 1 in {
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def STXVRL : XX1Form_memOp<31, 653, (outs),
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(ins vsrc:$XT, (memr $RA):$addr, g8rc:$RB),
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"stxvrl $XT, $addr, $RB", IIC_LdStLoad, []>;
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def STXVRLL : XX1Form_memOp<31, 685, (outs),
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(ins vsrc:$XT, (memr $RA):$addr, g8rc:$RB),
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"stxvrll $XT, $addr, $RB", IIC_LdStLoad, []>;
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def STXVPRL : XForm_XTp5_XAB5<31, 717, (outs),
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(ins vsrprc:$XTp, (memr $RA):$addr, g8rc:$RB),
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"stxvprl $XTp, $addr, $RB", IIC_LdStLFD, []>;
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def STXVPRLL
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: XForm_XTp5_XAB5<31, 749, (outs),
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(ins vsrprc:$XTp, (memr $RA):$addr, g8rc:$RB),
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"stxvprll $XTp, $addr, $RB", IIC_LdStLFD, []>;
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}
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def VUPKHSNTOB : VXForm_VRTB5<387, 0, (outs vrrc:$VRT), (ins vrrc:$VRB),
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"vupkhsntob $VRT, $VRB", []>;
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def VUPKLSNTOB : VXForm_VRTB5<387, 1, (outs vrrc:$VRT), (ins vrrc:$VRB),
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"vupklsntob $VRT, $VRB", []>;
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def VUPKINT4TOBF16
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: VXForm_VRTB5_UIM2<387, 2, (outs vrrc:$VRT), (ins vrrc:$VRB, u2imm:$UIM),
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"vupkint4tobf16 $VRT, $VRB, $UIM", []>;
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def VUPKINT8TOBF16
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: VXForm_VRTB5_UIM1<387, 1, (outs vrrc:$VRT), (ins vrrc:$VRB, u1imm:$UIM),
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"vupkint8tobf16 $VRT, $VRB, $UIM", []>;
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def VUPKINT8TOFP32
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: VXForm_VRTB5_UIM2<387, 3, (outs vrrc:$VRT), (ins vrrc:$VRB, u2imm:$UIM),
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"vupkint8tofp32 $VRT, $VRB, $UIM", []>;
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def VUPKINT4TOFP32
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: VXForm_VRTB5_UIM3<387, 2, (outs vrrc:$VRT), (ins vrrc:$VRB, u3imm:$UIM),
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"vupkint4tofp32 $VRT, $VRB, $UIM", []>;
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def VUCMPRHN : VXForm_VRTAB5<3, (outs vrrc:$VRT), (ins vrrc:$VRA, vrrc:$VRB),
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"vucmprhn $VRT, $VRA, $VRB", []>;
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def VUCMPRLN : VXForm_VRTAB5<67, (outs vrrc:$VRT), (ins vrrc:$VRA, vrrc:$VRB),
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"vucmprln $VRT, $VRA, $VRB", []>;
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def VUCMPRHB
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: VXForm_VRTAB5<131, (outs vrrc:$VRT), (ins vrrc:$VRA, vrrc:$VRB),
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"vucmprhb $VRT, $VRA, $VRB", []>;
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def VUCMPRLB
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: VXForm_VRTAB5<195, (outs vrrc:$VRT), (ins vrrc:$VRA, vrrc:$VRB),
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"vucmprlb $VRT, $VRA, $VRB", []>;
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def VUCMPRHH
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: VXForm_VRTAB5<259, (outs vrrc:$VRT), (ins vrrc:$VRA, vrrc:$VRB),
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"vucmprhh $VRT, $VRA, $VRB", []>;
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def VUCMPRLH
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: VXForm_VRTAB5<323, (outs vrrc:$VRT), (ins vrrc:$VRA, vrrc:$VRB),
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"vucmprlh $VRT, $VRA, $VRB", []>;
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}
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//---------------------------- Anonymous Patterns ----------------------------//
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// Load/Store VSX Vector with Right Length (Left-justified).
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def : Pat<(v4i32 (int_ppc_vsx_lxvrl addr:$RA, i64:$RB)), (LXVRL $RA, $RB)>;
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def : Pat<(v4i32 (int_ppc_vsx_lxvrll addr:$RA, i64:$RB)), (LXVRLL $RA, $RB)>;
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def : Pat<(int_ppc_vsx_stxvrl v4i32:$XT, addr:$RA, i64:$RB), (STXVRL $XT, $RA,
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$RB)>;
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def : Pat<(int_ppc_vsx_stxvrll v4i32:$XT, addr:$RA, i64:$RB), (STXVRLL $XT, $RA,
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$RB)>;
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// Load/Store VSX Vector pair with Right Length (Left-justified).
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def : Pat<(v256i1 (int_ppc_vsx_lxvprl addr:$RA, i64:$RB)), (LXVPRL $RA, $RB)>;
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def : Pat<(v256i1 (int_ppc_vsx_lxvprll addr:$RA, i64:$RB)), (LXVPRLL $RA, $RB)>;
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def : Pat<(int_ppc_vsx_stxvprl v256i1:$XTp, addr:$RA, i64:$RB), (STXVPRL $XTp,
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$RA, $RB)>;
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def : Pat<(int_ppc_vsx_stxvprll v256i1:$XTp, addr:$RA, i64:$RB), (STXVPRLL $XTp,
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$RA, $RB)>;
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