40270e8ef2
Cover all the missing cases and add very detailed tests for each rule. In summary: - Flat and Scratch, addrspace(0) and addrspace(5), loads are always divergent. - Global and Constant, addrspace(1) and addrspace(4), have real uniform loads, s_load, but require additional checks for align and flags in mmo. For not natural align or not uniform mmo do uniform-in-vgpr lowering. - Private, addrspace(3), only has instructions for divergent load, for uniform do uniform-in-vgpr lowering. - Store rules are simplified using Ptr32 and Ptr64. All operands need to be vgpr. Some tests have code size regression since they use more sgpr instructions, marked with FixMe comment to get back to later.
106 lines
4.3 KiB
LLVM
106 lines
4.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -mattr=-xnack < %s | FileCheck -check-prefixes=GFX9 %s
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; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX12 %s
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; Check lowering of some large extractelement that use the stack
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; instead of register indexing.
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define i32 @v_extract_v64i32_varidx(ptr addrspace(1) %ptr, i32 %idx) {
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; GFX9-LABEL: v_extract_v64i32_varidx:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX9-NEXT: v_and_b32_e32 v2, 63, v2
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; GFX9-NEXT: v_lshlrev_b32_e32 v2, 2, v2
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; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2
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; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
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; GFX9-NEXT: global_load_dword v0, v[0:1], off
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; GFX9-NEXT: s_waitcnt vmcnt(0)
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; GFX9-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX12-LABEL: v_extract_v64i32_varidx:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX12-NEXT: s_wait_expcnt 0x0
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; GFX12-NEXT: s_wait_samplecnt 0x0
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; GFX12-NEXT: s_wait_bvhcnt 0x0
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; GFX12-NEXT: s_wait_kmcnt 0x0
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; GFX12-NEXT: v_and_b32_e32 v2, 63, v2
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; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
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; GFX12-NEXT: v_lshlrev_b32_e32 v2, 2, v2
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; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2
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; GFX12-NEXT: s_wait_alu 0xfffd
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; GFX12-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
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; GFX12-NEXT: global_load_b32 v0, v[0:1], off
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; GFX12-NEXT: s_wait_loadcnt 0x0
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; GFX12-NEXT: s_setpc_b64 s[30:31]
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%vec = load <64 x i32>, ptr addrspace(1) %ptr
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%elt = extractelement <64 x i32> %vec, i32 %idx
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ret i32 %elt
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}
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define i16 @v_extract_v128i16_varidx(ptr addrspace(1) %ptr, i32 %idx) {
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; GFX9-LABEL: v_extract_v128i16_varidx:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX9-NEXT: v_and_b32_e32 v2, 0x7f, v2
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; GFX9-NEXT: v_lshlrev_b32_e32 v2, 1, v2
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; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2
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; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
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; GFX9-NEXT: global_load_ushort v0, v[0:1], off
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; GFX9-NEXT: s_waitcnt vmcnt(0)
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; GFX9-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX12-LABEL: v_extract_v128i16_varidx:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX12-NEXT: s_wait_expcnt 0x0
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; GFX12-NEXT: s_wait_samplecnt 0x0
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; GFX12-NEXT: s_wait_bvhcnt 0x0
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; GFX12-NEXT: s_wait_kmcnt 0x0
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; GFX12-NEXT: v_and_b32_e32 v2, 0x7f, v2
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; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
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; GFX12-NEXT: v_lshlrev_b32_e32 v2, 1, v2
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; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2
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; GFX12-NEXT: s_wait_alu 0xfffd
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; GFX12-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
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; GFX12-NEXT: global_load_u16 v0, v[0:1], off
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; GFX12-NEXT: s_wait_loadcnt 0x0
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; GFX12-NEXT: s_setpc_b64 s[30:31]
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%vec = load <128 x i16>, ptr addrspace(1) %ptr
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%elt = extractelement <128 x i16> %vec, i32 %idx
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ret i16 %elt
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}
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define i64 @v_extract_v32i64_varidx(ptr addrspace(1) %ptr, i32 %idx) {
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; GFX9-LABEL: v_extract_v32i64_varidx:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX9-NEXT: v_and_b32_e32 v2, 31, v2
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; GFX9-NEXT: v_lshlrev_b32_e32 v2, 3, v2
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; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2
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; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
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; GFX9-NEXT: global_load_dwordx2 v[0:1], v[0:1], off
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; GFX9-NEXT: s_waitcnt vmcnt(0)
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; GFX9-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX12-LABEL: v_extract_v32i64_varidx:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX12-NEXT: s_wait_expcnt 0x0
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; GFX12-NEXT: s_wait_samplecnt 0x0
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; GFX12-NEXT: s_wait_bvhcnt 0x0
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; GFX12-NEXT: s_wait_kmcnt 0x0
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; GFX12-NEXT: v_and_b32_e32 v2, 31, v2
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; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
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; GFX12-NEXT: v_lshlrev_b32_e32 v2, 3, v2
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; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2
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; GFX12-NEXT: s_wait_alu 0xfffd
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; GFX12-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
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; GFX12-NEXT: global_load_b64 v[0:1], v[0:1], off
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; GFX12-NEXT: s_wait_loadcnt 0x0
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; GFX12-NEXT: s_setpc_b64 s[30:31]
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%vec = load <32 x i64>, ptr addrspace(1) %ptr
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%elt = extractelement <32 x i64> %vec, i32 %idx
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ret i64 %elt
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}
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