98 lines
3.8 KiB
TableGen
98 lines
3.8 KiB
TableGen
// RUN: llvm-tblgen -gen-disassembler -I %p/../../../include %s | FileCheck %s --check-prefixes=CHECK,CHECK-SMALL
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// RUN: llvm-tblgen -gen-disassembler --large-decoder-table -I %p/../../../include %s | FileCheck %s --check-prefixes=CHECK,CHECK-LARGE
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include "llvm/Target/Target.td"
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def ArchInstrInfo : InstrInfo { }
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def Arch : Target {
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let InstructionSet = ArchInstrInfo;
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}
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def Reg : Register<"reg">;
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def RegClass : RegisterClass<"foo", [i64], 0, (add Reg)>;
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def GR64 : RegisterOperand<RegClass>;
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class MyMemOperand<dag sub_ops> : Operand<iPTR> {
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let MIOperandInfo = sub_ops;
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dag Base;
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dag Extension;
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}
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def MemOp16: MyMemOperand<(ops GR64:$reg, i16imm:$offset)>;
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def MemOp32: MyMemOperand<(ops GR64:$reg, i32imm:$offset)>;
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class MyVarInst<MyMemOperand memory_op> : Instruction {
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dag Inst;
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let OutOperandList = (outs GR64:$dst);
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let InOperandList = (ins memory_op:$src);
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}
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def FOO16 : MyVarInst<MemOp16> {
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let Inst = (ascend
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(descend (operand "$dst", 3), 0b01000, (operand "$src.reg", 3)),
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(slice "$src.offset", 15, 0, (decoder "myCustomDecoder"))
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);
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}
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def FOO32 : MyVarInst<MemOp32> {
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let Inst = (ascend
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(descend (operand "$dst", 3), 0b01001,
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(operand "$src.reg", 3, (decoder "myCustomDecoder"))),
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(slice "$src.offset", 31, 16),
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(slice "$src.offset", 15, 0)
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);
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}
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// Instruction length table
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// CHECK: InstrLenTable
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// CHECK: 27,
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// CHECK-NEXT: 43,
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// CHECK-NEXT: };
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// CHECK-SMALL: /* 0 */ OPC_ExtractField, 3, 5, // Field = Inst{7-3}
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// CHECK-SMALL-NEXT: /* 3 */ OPC_FilterValueOrSkip, 8, 4, 0, // if Field != 0x8 skip to 11
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// CHECK-SMALL-NEXT: /* 7 */ OPC_Decode, {{[0-9]+}}, {{[0-9]+}}, 0, // Opcode: FOO16
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// CHECK-SMALL-NEXT: /* 11 */ OPC_FilterValue, 9, // if Field != 0x9 pop scope
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// CHECK-SMALL-NEXT: /* 13 */ OPC_Decode, {{[0-9]+}}, {{[0-9]+}}, 1, // Opcode: FOO32
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// CHECK-SMALL-NEXT: };
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// CHECK-LARGE: /* 0 */ OPC_ExtractField, 3, 5, // Field = Inst{7-3}
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// CHECK-LARGE-NEXT: /* 3 */ OPC_FilterValueOrSkip, 8, 4, 0, 0, // if Field != 0x8 skip to 12
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// CHECK-LARGE-NEXT: /* 8 */ OPC_Decode, {{[0-9]+}}, {{[0-9]+}}, 0, // Opcode: FOO16
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// CHECK-LARGE-NEXT: /* 12 */ OPC_FilterValue, 9, // if Field != 0x9 pop scope
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// CHECK-LARGE-NEXT: /* 14 */ OPC_Decode, {{[0-9]+}}, {{[0-9]+}}, 1, // Opcode: FOO32
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// CHECK-LARGE-NEXT: };
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// CHECK: case 0:
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// CHECK-NEXT: tmp = fieldFromInstruction(insn, 8, 3);
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// CHECK-NEXT: if (!Check(S, DecodeRegClassRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
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// CHECK-NEXT: tmp = fieldFromInstruction(insn, 0, 3);
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// CHECK-NEXT: if (!Check(S, DecodeRegClassRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
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// CHECK-NEXT: tmp = fieldFromInstruction(insn, 11, 16);
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// CHECK-NEXT: if (!Check(S, myCustomDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
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// CHECK-NEXT: return S;
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// CHECK-NEXT: case 1:
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// CHECK-NEXT: tmp = fieldFromInstruction(insn, 8, 3);
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// CHECK-NEXT: if (!Check(S, DecodeRegClassRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
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// CHECK-NEXT: tmp = fieldFromInstruction(insn, 0, 3);
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// CHECK-NEXT: if (!Check(S, myCustomDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
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// CHECK-NEXT: tmp = 0x0;
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// CHECK-NEXT: tmp |= fieldFromInstruction(insn, 11, 16) << 16;
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// CHECK-NEXT: tmp |= fieldFromInstruction(insn, 27, 16);
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// CHECK-NEXT: MI.addOperand(MCOperand::createImm(tmp));
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// CHECK-NEXT: return S;
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// CHECK-LABEL: case OPC_ExtractField: {
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// CHECK: makeUp(insn, Start + Len);
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// CHECK-LABEL: case OPC_CheckField: {
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// CHECK: makeUp(insn, Start + Len);
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// CHECK-LABEL: case OPC_Decode: {
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// CHECK: Len = InstrLenTable[Opc];
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// CHECK-NEXT: makeUp(insn, Len);
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