7f4c297e94
`Predicates` and `Features` fields serve the same purpose. They should be kept in sync, but not all predicates are based on features. This resulted in introducing dummy features for that only reason. This patch removes `Features` field and changes TableGen emitters to use `Predicates` instead. Historically, predicates were written with the assumption that the checking code will be used in `SelectionDAGISel` subclasses, meaning they will have access to the subclass variables, such as `Subtarget`. There are no such variables in the generated `GenSubtargetInfo::getHwModeSet()`, so we need to provide them. This can be achieved by subclassing `HwModePredicateProlog`, see an example in `Hexagon.td`.
93 lines
2.3 KiB
TableGen
93 lines
2.3 KiB
TableGen
// RUN: llvm-tblgen -gen-emitter -I %p/../../include %s | FileCheck %s --check-prefix=ENCODER
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// RUN: llvm-tblgen -gen-disassembler -I %p/../../include %s | FileCheck %s --check-prefix=DECODER
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include "llvm/Target/Target.td"
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def archInstrInfo : InstrInfo { }
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def arch : Target {
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let InstructionSet = archInstrInfo;
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}
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def Myi32 : Operand<i32> {
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let DecoderMethod = "DecodeMyi32";
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}
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def HasA : Predicate<"Subtarget->hasA()">;
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def HasB : Predicate<"Subtarget->hasB()">;
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def ModeA : HwMode<[HasA]>;
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def ModeB : HwMode<[HasB]>;
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def fooTypeEncA : InstructionEncoding {
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let Size = 4;
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field bits<32> SoftFail = 0;
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bits<32> Inst;
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bits<8> factor;
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let Inst{7...0} = factor;
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let Inst{3...2} = 0b11;
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let Inst{1...0} = 0b00;
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}
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def fooTypeEncB : InstructionEncoding {
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let Size = 4;
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field bits<32> SoftFail = 0;
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bits<32> Inst;
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bits<8> factor;
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let Inst{15...8} = factor;
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let Inst{1...0} = 0b11;
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}
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let OutOperandList = (outs) in {
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def foo : Instruction {
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let InOperandList = (ins i32imm:$factor);
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let EncodingInfos = EncodingByHwMode<
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[ModeA, ModeB], [fooTypeEncA,
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fooTypeEncB]
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>;
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let AsmString = "foo $factor";
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}
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def bar: Instruction {
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let InOperandList = (ins i32imm:$factor);
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let Size = 4;
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bits<32> Inst;
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bits<32> SoftFail;
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bits<8> factor;
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let Inst{31...24} = factor;
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let Inst{1...0} = 0b10;
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let AsmString = "bar $factor";
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}
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def baz : Instruction {
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let InOperandList = (ins i32imm:$factor);
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bits<32> Inst;
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let EncodingInfos = EncodingByHwMode<
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[ModeB], [fooTypeEncA]
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>;
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let AsmString = "foo $factor";
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}
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}
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// DECODER-LABEL: DecoderTable_ModeA32
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// DECODER-DAG: Opcode: fooTypeEncA:foo
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// DECODER-DAG: Opcode: bar
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// DECODER-LABEL: DecoderTable_ModeB32
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// DECODER-DAG: Opcode: fooTypeEncB:foo
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// DECODER-DAG: Opcode: fooTypeEncA:baz
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// DECODER-DAG: Opcode: bar
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// ENCODER-LABEL: static const uint64_t InstBits_ModeA[] = {
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// ENCODER: UINT64_C(2), // bar
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// ENCODER: UINT64_C(12), // foo
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// ENCODER-LABEL: static const uint64_t InstBits_ModeB[] = {
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// ENCODER: UINT64_C(2), // bar
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// ENCODER: UINT64_C(3), // foo
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// ENCODER: case ::foo: {
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// ENCODER: switch (HwMode) {
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// ENCODER: default: llvm_unreachable("Unhandled HwMode");
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// ENCODER: case 1: {
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