a57847232f
The tests in this directory all depend on the AMDGPU target being present so we can let opt infer the data layout. Reviewed By: arsenm Pull Request: https://github.com/llvm/llvm-project/pull/137924
138 lines
5.3 KiB
LLVM
138 lines
5.3 KiB
LLVM
; RUN: opt -S -mtriple=amdgcn--amdhsa -passes=load-store-vectorizer < %s | FileCheck %s
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; RUN: opt -S -mtriple=amdgcn--amdhsa -passes='function(load-store-vectorizer)' < %s | FileCheck %s
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; Check that vectorizer can find a GEP through bitcast
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; CHECK-LABEL: @vect_zext_bitcast_f32_to_i32_idx
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; CHECK: load <4 x i32>
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define void @vect_zext_bitcast_f32_to_i32_idx(ptr addrspace(1) %arg1, i32 %base) {
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%add1 = add nuw i32 %base, 0
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%zext1 = zext i32 %add1 to i64
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%gep1 = getelementptr inbounds float, ptr addrspace(1) %arg1, i64 %zext1
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%load1 = load i32, ptr addrspace(1) %gep1, align 4
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%add2 = add nuw i32 %base, 1
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%zext2 = zext i32 %add2 to i64
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%gep2 = getelementptr inbounds float, ptr addrspace(1) %arg1, i64 %zext2
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%load2 = load i32, ptr addrspace(1) %gep2, align 4
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%add3 = add nuw i32 %base, 2
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%zext3 = zext i32 %add3 to i64
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%gep3 = getelementptr inbounds float, ptr addrspace(1) %arg1, i64 %zext3
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%load3 = load i32, ptr addrspace(1) %gep3, align 4
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%add4 = add nuw i32 %base, 3
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%zext4 = zext i32 %add4 to i64
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%gep4 = getelementptr inbounds float, ptr addrspace(1) %arg1, i64 %zext4
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%load4 = load i32, ptr addrspace(1) %gep4, align 4
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ret void
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}
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; CHECK-LABEL: @vect_zext_bitcast_i8_st1_to_i32_idx
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; CHECK: load i32
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; CHECK: load i32
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; CHECK: load i32
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; CHECK: load i32
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define void @vect_zext_bitcast_i8_st1_to_i32_idx(ptr addrspace(1) %arg1, i32 %base) {
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%add1 = add nuw i32 %base, 0
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%zext1 = zext i32 %add1 to i64
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%gep1 = getelementptr inbounds i8, ptr addrspace(1) %arg1, i64 %zext1
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%load1 = load i32, ptr addrspace(1) %gep1, align 4
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%add2 = add nuw i32 %base, 1
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%zext2 = zext i32 %add2 to i64
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%gep2 = getelementptr inbounds i8,ptr addrspace(1) %arg1, i64 %zext2
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%load2 = load i32, ptr addrspace(1) %gep2, align 4
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%add3 = add nuw i32 %base, 2
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%zext3 = zext i32 %add3 to i64
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%gep3 = getelementptr inbounds i8, ptr addrspace(1) %arg1, i64 %zext3
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%load3 = load i32, ptr addrspace(1) %gep3, align 4
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%add4 = add nuw i32 %base, 3
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%zext4 = zext i32 %add4 to i64
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%gep4 = getelementptr inbounds i8, ptr addrspace(1) %arg1, i64 %zext4
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%load4 = load i32, ptr addrspace(1) %gep4, align 4
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ret void
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}
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; CHECK-LABEL: @vect_zext_bitcast_i8_st4_to_i32_idx
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; CHECK: load <4 x i32>
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define void @vect_zext_bitcast_i8_st4_to_i32_idx(ptr addrspace(1) %arg1, i32 %base) {
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%add1 = add nuw i32 %base, 0
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%zext1 = zext i32 %add1 to i64
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%gep1 = getelementptr inbounds i8, ptr addrspace(1) %arg1, i64 %zext1
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%load1 = load i32, ptr addrspace(1) %gep1, align 4
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%add2 = add nuw i32 %base, 4
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%zext2 = zext i32 %add2 to i64
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%gep2 = getelementptr inbounds i8,ptr addrspace(1) %arg1, i64 %zext2
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%load2 = load i32, ptr addrspace(1) %gep2, align 4
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%add3 = add nuw i32 %base, 8
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%zext3 = zext i32 %add3 to i64
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%gep3 = getelementptr inbounds i8, ptr addrspace(1) %arg1, i64 %zext3
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%load3 = load i32, ptr addrspace(1) %gep3, align 4
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%add4 = add nuw i32 %base, 12
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%zext4 = zext i32 %add4 to i64
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%gep4 = getelementptr inbounds i8, ptr addrspace(1) %arg1, i64 %zext4
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%load4 = load i32, ptr addrspace(1) %gep4, align 4
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ret void
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}
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; CHECK-LABEL: @vect_zext_bitcast_negative_ptr_delta
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; CHECK: load <2 x i32>
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define void @vect_zext_bitcast_negative_ptr_delta(ptr addrspace(1) %p, i32 %base) {
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%a.offset = add nuw i32 %base, 4
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%t.offset.zexted = zext i32 %base to i64
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%a.offset.zexted = zext i32 %a.offset to i64
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%t.ptr = getelementptr inbounds i16, ptr addrspace(1) %p, i64 %t.offset.zexted
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%a.ptr = getelementptr inbounds i16, ptr addrspace(1) %p, i64 %a.offset.zexted
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%b.ptr = getelementptr inbounds i16, ptr addrspace(1) %t.ptr, i64 6
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%a.val = load i32, ptr addrspace(1) %a.ptr
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%b.val = load i32, ptr addrspace(1) %b.ptr
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ret void
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}
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; Check i1 corner case
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; CHECK-LABEL: @zexted_i1_gep_index
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; CHECK: load i32
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; CHECK: load i32
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define void @zexted_i1_gep_index(ptr addrspace(1) %p, i32 %val) {
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%selector = icmp eq i32 %val, 0
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%flipped = xor i1 %selector, 1
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%index.0 = zext i1 %selector to i64
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%index.1 = zext i1 %flipped to i64
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%gep.0 = getelementptr inbounds i32, ptr addrspace(1) %p, i64 %index.0
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%gep.1 = getelementptr inbounds i32, ptr addrspace(1) %p, i64 %index.1
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%val0 = load i32, ptr addrspace(1) %gep.0
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%val1 = load i32, ptr addrspace(1) %gep.1
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ret void
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}
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; Check i1 corner case
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; CHECK-LABEL: @sexted_i1_gep_index
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; CHECK: load i32
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; CHECK: load i32
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define void @sexted_i1_gep_index(ptr addrspace(1) %p, i32 %val) {
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%selector = icmp eq i32 %val, 0
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%flipped = xor i1 %selector, 1
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%index.0 = sext i1 %selector to i64
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%index.1 = sext i1 %flipped to i64
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%gep.0 = getelementptr inbounds i32, ptr addrspace(1) %p, i64 %index.0
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%gep.1 = getelementptr inbounds i32, ptr addrspace(1) %p, i64 %index.1
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%val0 = load i32, ptr addrspace(1) %gep.0
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%val1 = load i32, ptr addrspace(1) %gep.1
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ret void
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}
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; CHECK-LABEL: @zexted_i1_gep_index_different_bbs
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; CHECK: load i32
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; CHECK: load i32
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define void @zexted_i1_gep_index_different_bbs(ptr addrspace(1) %p, i32 %val) {
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entry:
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%selector = icmp eq i32 %val, 0
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%flipped = xor i1 %selector, 1
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%index.0 = zext i1 %selector to i64
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%index.1 = zext i1 %flipped to i64
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%gep.0 = getelementptr inbounds i32, ptr addrspace(1) %p, i64 %index.0
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br label %next
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next:
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%gep.1 = getelementptr inbounds i32, ptr addrspace(1) %p, i64 %index.1
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%val0 = load i32, ptr addrspace(1) %gep.0
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%val1 = load i32, ptr addrspace(1) %gep.1
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ret void
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}
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