50b9ca4dda
After https://github.com/llvm/llvm-project/pull/153643, there may be a BranchOnCond with constant condition in the entry block. Simplify those in removeBranchOnConst. This removes a number of redundant conditional branch from entry blocks. In some cases, it may also make the original scalar loop unreachable, because we know it will never execute. In that case, we need to remove the loop from LoopInfo, because all unreachable blocks may dominate each other, making LoopInfo invalid. In those cases, we can also completely remove the loop, for which I'll share a follow-up patch. Depends on https://github.com/llvm/llvm-project/pull/153643. PR: https://github.com/llvm/llvm-project/pull/154510
99 lines
4.1 KiB
LLVM
99 lines
4.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
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; RUN: opt -p loop-vectorize -S %s | FileCheck %s
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target triple = "arm64-apple-macosx"
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; Test case for https://github.com/llvm/llvm-project/issues/107015.
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define i64 @mul_select_operand_known_1_via_scev() {
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; CHECK-LABEL: define i64 @mul_select_operand_known_1_via_scev() {
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; CHECK-NEXT: [[ENTRY:.*]]:
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; CHECK-NEXT: br label %[[LOOP:.*]]
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; CHECK: [[LOOP]]:
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; CHECK-NEXT: [[RED:%.*]] = phi i64 [ 12, %[[ENTRY]] ], [ [[RED_NEXT:%.*]], %[[LOOP]] ]
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; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
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; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[IV]], 1
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; CHECK-NEXT: [[CMP1_I:%.*]] = icmp eq i32 [[TMP1]], 0
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; CHECK-NEXT: [[NARROW_I:%.*]] = select i1 [[CMP1_I]], i32 1, i32 [[IV]]
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; CHECK-NEXT: [[MUL:%.*]] = zext nneg i32 [[NARROW_I]] to i64
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; CHECK-NEXT: [[RED_NEXT]] = mul nsw i64 [[RED]], [[MUL]]
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; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
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; CHECK-NEXT: [[EC:%.*]] = icmp eq i32 [[IV]], 1
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; CHECK-NEXT: br i1 [[EC]], label %[[EXIT:.*]], label %[[LOOP]]
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; CHECK: [[EXIT]]:
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; CHECK-NEXT: [[RES:%.*]] = phi i64 [ [[RED_NEXT]], %[[LOOP]] ]
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; CHECK-NEXT: ret i64 [[RES]]
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;
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entry:
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br label %loop
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loop:
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%red = phi i64 [ 12, %entry ], [ %red.next, %loop ]
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%iv = phi i32 [ 0, %entry ], [ %iv.next, %loop ]
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%0 = and i32 %iv, 1
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%cmp1.i = icmp eq i32 %0, 0
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%narrow.i = select i1 %cmp1.i, i32 1, i32 %iv
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%mul = zext nneg i32 %narrow.i to i64
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%red.next = mul nsw i64 %red, %mul
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%iv.next = add nuw nsw i32 %iv, 1
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%ec = icmp eq i32 %iv, 1
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br i1 %ec, label %exit, label %loop
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exit:
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%res = phi i64 [ %red.next, %loop ]
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ret i64 %res
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}
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define i32 @add_reduction_select_operand_constant_but_non_uniform() {
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; CHECK-LABEL: define i32 @add_reduction_select_operand_constant_but_non_uniform() {
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; CHECK-NEXT: [[ENTRY:.*:]]
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; CHECK-NEXT: br label %[[VECTOR_PH:.*]]
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; CHECK: [[VECTOR_PH]]:
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; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
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; CHECK: [[VECTOR_BODY]]:
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; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
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; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ <i32 42, i32 0, i32 0, i32 0>, %[[VECTOR_PH]] ], [ [[TMP2:%.*]], %[[VECTOR_BODY]] ]
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; CHECK-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP1:%.*]], %[[VECTOR_BODY]] ]
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; CHECK-NEXT: [[TMP2]] = add <4 x i32> zeroinitializer, [[VEC_PHI]]
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; CHECK-NEXT: [[TMP1]] = add <4 x i32> zeroinitializer, [[VEC_PHI1]]
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; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 8
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; CHECK-NEXT: [[TMP0:%.*]] = icmp eq i32 [[INDEX_NEXT]], 64
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; CHECK-NEXT: br i1 [[TMP0]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
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; CHECK: [[MIDDLE_BLOCK]]:
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; CHECK-NEXT: [[BIN_RDX:%.*]] = add <4 x i32> [[TMP1]], [[TMP2]]
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; CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[BIN_RDX]])
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; CHECK-NEXT: br label %[[EXIT:.*]]
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; CHECK: [[SCALAR_PH:.*]]:
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; CHECK-NEXT: br label %[[LOOP:.*]]
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; CHECK: [[LOOP]]:
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; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, %[[SCALAR_PH]] ], [ [[ADD2_REASS:%.*]], %[[LOOP]] ]
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; CHECK-NEXT: [[RDX:%.*]] = phi i32 [ 42, %[[SCALAR_PH]] ], [ [[RDX_NEXT:%.*]], %[[LOOP]] ]
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; CHECK-NEXT: [[ADD2_REASS]] = add i32 [[IV]], 1
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; CHECK-NEXT: [[RDX_NEXT]] = add i32 0, [[RDX]]
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; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[ADD2_REASS]], 64
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; CHECK-NEXT: br i1 [[CMP]], label %[[LOOP]], label %[[EXIT]]
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; CHECK: [[EXIT]]:
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; CHECK-NEXT: [[ADD_LCSSA:%.*]] = phi i32 [ [[RDX_NEXT]], %[[LOOP]] ], [ [[TMP3]], %[[MIDDLE_BLOCK]] ]
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; CHECK-NEXT: ret i32 [[ADD_LCSSA]]
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;
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entry:
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br label %loop
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loop:
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%iv = phi i32 [ 0, %entry ], [ %iv.next, %loop ]
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%rdx = phi i32 [ 42, %entry ], [ %rdx.next, %loop ]
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%iv.next = add i32 %iv, 1
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%rdx.next = add i32 0, %rdx
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%cmp = icmp ult i32 %iv.next, 64
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br i1 %cmp, label %loop, label %exit
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exit:
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ret i32 %rdx.next
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}
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;.
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; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}
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; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}
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; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}
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;.
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