50b9ca4dda
After https://github.com/llvm/llvm-project/pull/153643, there may be a BranchOnCond with constant condition in the entry block. Simplify those in removeBranchOnConst. This removes a number of redundant conditional branch from entry blocks. In some cases, it may also make the original scalar loop unreachable, because we know it will never execute. In that case, we need to remove the loop from LoopInfo, because all unreachable blocks may dominate each other, making LoopInfo invalid. In those cases, we can also completely remove the loop, for which I'll share a follow-up patch. Depends on https://github.com/llvm/llvm-project/pull/153643. PR: https://github.com/llvm/llvm-project/pull/154510
88 lines
4.2 KiB
LLVM
88 lines
4.2 KiB
LLVM
; RUN: opt -mtriple=thumbv8.1m.main-arm-eabihf -mattr=+mve.fp -passes=loop-vectorize -tail-predication=enabled -S < %s | \
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; RUN: FileCheck %s
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target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
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; Check that loop hint predicate.enable loop can overrule the TTI hook. For
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; this test case, the TTI hook rejects tail-predication:
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;
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; ARMHWLoops: Trip count does not fit into 32bits
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; preferPredicateOverEpilogue: hardware-loop is not profitable.
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;
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define dso_local void @tail_folding(ptr noalias nocapture %A, ptr noalias nocapture readonly %B, ptr noalias nocapture readonly %C) {
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; CHECK-LABEL: tail_folding(
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; CHECK: vector.body:
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; CHECK-NOT: call <4 x i32> @llvm.masked.load.v4i32.p0(
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; CHECK-NOT: call void @llvm.masked.store.v4i32.p0(
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; CHECK: br i1 %{{.*}}, label %{{.*}}, label %vector.body, !llvm.loop [[VEC_LOOP1:![0-9]+]]
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;
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; CHECK: br i1 %{{.*}}, label %{{.*}}, label %for.body, !llvm.loop [[SCALAR_LOOP1:![0-9]+]]
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entry:
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br label %for.body
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for.cond.cleanup:
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ret void
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for.body:
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%indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
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%arrayidx = getelementptr inbounds i32, ptr %B, i64 %indvars.iv
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%0 = load i32, ptr %arrayidx, align 4
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%arrayidx2 = getelementptr inbounds i32, ptr %C, i64 %indvars.iv
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%1 = load i32, ptr %arrayidx2, align 4
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%add = add nsw i32 %1, %0
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%arrayidx4 = getelementptr inbounds i32, ptr %A, i64 %indvars.iv
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store i32 %add, ptr %arrayidx4, align 4
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%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
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%exitcond = icmp eq i64 %indvars.iv.next, 430
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br i1 %exitcond, label %for.cond.cleanup, label %for.body
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}
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; The same test case but now with predicate.enable = true should get
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; tail-folded.
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;
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define dso_local void @predicate_loop_hint(ptr noalias nocapture %A, ptr noalias nocapture readonly %B, ptr noalias nocapture readonly %C) {
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; CHECK-LABEL: predicate_loop_hint(
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; CHECK: vector.body:
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; CHECK: %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
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; CHECK: %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i64(i64 %index, i64 430)
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; CHECK: %[[WML1:.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0({{.*}}<4 x i1> %active.lane.mask
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; CHECK: %[[WML2:.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0({{.*}}<4 x i1> %active.lane.mask
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; CHECK: %[[ADD:.*]] = add nsw <4 x i32> %[[WML2]], %[[WML1]]
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; CHECK: call void @llvm.masked.store.v4i32.p0(<4 x i32> %[[ADD]], {{.*}}<4 x i1> %active.lane.mask
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; CHECK: %index.next = add nuw i64 %index, 4
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; CHECK: br i1 %{{.*}}, label %{{.*}}, label %vector.body, !llvm.loop [[VEC_LOOP2:![0-9]+]]
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;
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; CHECK: br i1 %{{.*}}, label %{{.*}}, label %for.body, !llvm.loop [[SCALAR_LOOP2:![0-9]+]]
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entry:
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br label %for.body
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for.cond.cleanup:
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ret void
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for.body:
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%indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
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%arrayidx = getelementptr inbounds i32, ptr %B, i64 %indvars.iv
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%0 = load i32, ptr %arrayidx, align 4
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%arrayidx2 = getelementptr inbounds i32, ptr %C, i64 %indvars.iv
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%1 = load i32, ptr %arrayidx2, align 4
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%add = add nsw i32 %1, %0
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%arrayidx4 = getelementptr inbounds i32, ptr %A, i64 %indvars.iv
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store i32 %add, ptr %arrayidx4, align 4
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%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
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%exitcond = icmp eq i64 %indvars.iv.next, 430
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br i1 %exitcond, label %for.cond.cleanup, label %for.body, !llvm.loop !6
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}
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; CHECK: [[VEC_LOOP1]] = distinct !{[[VEC_LOOP1]], [[MD_IS_VEC:![0-9]+]], [[MD_RT_UNROLL_DIS:![0-9]+]]}
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; CHECK-NEXT: [[MD_IS_VEC:![0-9]+]] = !{!"llvm.loop.isvectorized", i32 1}
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; CHECK-NEXT: [[MD_RT_UNROLL_DIS]] = !{!"llvm.loop.unroll.runtime.disable"}
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; CHECK-NEXT: [[SCALAR_LOOP1]] = distinct !{[[SCALAR_LOOP1]], [[MD_RT_UNROLL_DIS]], [[MD_IS_VEC]]}
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; CHECK-NEXT: [[VEC_LOOP2]] = distinct !{[[VEC_LOOP2]], [[MD_IS_VEC]], [[MD_RT_UNROLL_DIS]]}
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; CHECK-NEXT: [[SCALAR_LOOP2]] = distinct !{[[SCALAR_LOOP2]], [[ORIG_PRED_ENABLED:!.+]], [[ORIG_VEC_ENABLED:!.+]]}
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; CHECK-NEXT: [[ORIG_PRED_ENABLED]] = !{!"llvm.loop.vectorize.predicate.enable", i1 true}
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; CHECK-NEXT: [[ORIG_VEC_ENABLED]] = !{!"llvm.loop.vectorize.enable", i1 true}
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!6 = distinct !{!6, !7, !8}
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!7 = !{!"llvm.loop.vectorize.predicate.enable", i1 true}
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!8 = !{!"llvm.loop.vectorize.enable", i1 true}
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