50b9ca4dda
After https://github.com/llvm/llvm-project/pull/153643, there may be a BranchOnCond with constant condition in the entry block. Simplify those in removeBranchOnConst. This removes a number of redundant conditional branch from entry blocks. In some cases, it may also make the original scalar loop unreachable, because we know it will never execute. In that case, we need to remove the loop from LoopInfo, because all unreachable blocks may dominate each other, making LoopInfo invalid. In those cases, we can also completely remove the loop, for which I'll share a follow-up patch. Depends on https://github.com/llvm/llvm-project/pull/153643. PR: https://github.com/llvm/llvm-project/pull/154510
127 lines
7.0 KiB
LLVM
127 lines
7.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
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; RUN: opt -passes=loop-vectorize \
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; RUN: -prefer-predicate-over-epilogue=predicate-else-scalar-epilogue \
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; RUN: -mtriple=riscv64 -mattr=+v -S < %s | FileCheck %s
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; Make sure we do not vectorize a loop with a widened int induction.
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define void @test_wide_integer_induction(ptr noalias %a, i64 %N) {
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; CHECK-LABEL: define void @test_wide_integer_induction(
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; CHECK-SAME: ptr noalias [[A:%.*]], i64 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[ENTRY:%.*]]
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; CHECK: vector.ph:
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; CHECK-NEXT: [[TMP9:%.*]] = call <vscale x 2 x i64> @llvm.stepvector.nxv2i64()
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; CHECK-NEXT: [[TMP10:%.*]] = mul <vscale x 2 x i64> [[TMP9]], splat (i64 1)
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; CHECK-NEXT: [[INDUCTION:%.*]] = add <vscale x 2 x i64> zeroinitializer, [[TMP10]]
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; CHECK-NEXT: br label [[FOR_BODY:%.*]]
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; CHECK: vector.body:
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; CHECK-NEXT: [[EVL_BASED_IV:%.*]] = phi i64 [ 0, [[ENTRY]] ], [ [[INDEX_EVL_NEXT:%.*]], [[FOR_BODY]] ]
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; CHECK-NEXT: [[VEC_IND:%.*]] = phi <vscale x 2 x i64> [ [[INDUCTION]], [[ENTRY]] ], [ [[VEC_IND_NEXT:%.*]], [[FOR_BODY]] ]
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; CHECK-NEXT: [[AVL:%.*]] = phi i64 [ [[N]], [[ENTRY]] ], [ [[AVL_NEXT:%.*]], [[FOR_BODY]] ]
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; CHECK-NEXT: [[TMP11:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 2, i1 true)
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; CHECK-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64
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; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 2 x i64> poison, i64 [[TMP12]], i64 0
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; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 2 x i64> [[BROADCAST_SPLATINSERT]], <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
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; CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[EVL_BASED_IV]]
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; CHECK-NEXT: call void @llvm.vp.store.nxv2i64.p0(<vscale x 2 x i64> [[VEC_IND]], ptr align 8 [[TMP14]], <vscale x 2 x i1> splat (i1 true), i32 [[TMP11]])
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; CHECK-NEXT: [[TMP16:%.*]] = zext i32 [[TMP11]] to i64
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; CHECK-NEXT: [[INDEX_EVL_NEXT]] = add i64 [[TMP16]], [[EVL_BASED_IV]]
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; CHECK-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP16]]
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; CHECK-NEXT: [[VEC_IND_NEXT]] = add <vscale x 2 x i64> [[VEC_IND]], [[BROADCAST_SPLAT]]
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; CHECK-NEXT: [[TMP15:%.*]] = icmp eq i64 [[AVL_NEXT]], 0
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; CHECK-NEXT: br i1 [[TMP15]], label [[MIDDLE_BLOCK:%.*]], label [[FOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
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; CHECK: middle.block:
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; CHECK-NEXT: br label [[FOR_COND_CLEANUP:%.*]]
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; CHECK: scalar.ph:
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; CHECK-NEXT: br label [[FOR_BODY1:%.*]]
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; CHECK: for.body:
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; CHECK-NEXT: [[IV1:%.*]] = phi i64 [ 0, [[SCALAR_PH:%.*]] ], [ [[IV_NEXT1:%.*]], [[FOR_BODY1]] ]
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; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[IV1]]
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; CHECK-NEXT: store i64 [[IV1]], ptr [[ARRAYIDX]], align 8
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; CHECK-NEXT: [[IV_NEXT1]] = add nuw nsw i64 [[IV1]], 1
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; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT1]], [[N]]
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; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_COND_CLEANUP]], label [[FOR_BODY1]]
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; CHECK: for.cond.cleanup:
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; CHECK-NEXT: ret void
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;
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entry:
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br label %for.body
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for.body:
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%iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
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%arrayidx = getelementptr inbounds i64, ptr %a, i64 %iv
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store i64 %iv, ptr %arrayidx, align 8
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%iv.next = add nuw nsw i64 %iv, 1
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%exitcond.not = icmp eq i64 %iv.next, %N
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br i1 %exitcond.not, label %for.cond.cleanup, label %for.body
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for.cond.cleanup:
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ret void
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}
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; Make sure we do not vectorize a loop with a widened ptr induction.
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define void @test_wide_ptr_induction(ptr noalias %a, ptr noalias %b, i64 %N) {
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; CHECK-LABEL: define void @test_wide_ptr_induction(
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; CHECK-SAME: ptr noalias [[A:%.*]], ptr noalias [[B:%.*]], i64 [[N:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[VECTOR_PH:%.*]]
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; CHECK: vector.ph:
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; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
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; CHECK: vector.body:
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; CHECK-NEXT: [[EVL_BASED_IV:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_EVL_NEXT:%.*]], [[VECTOR_BODY]] ]
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; CHECK-NEXT: [[POINTER_PHI:%.*]] = phi ptr [ [[B]], [[VECTOR_PH]] ], [ [[PTR_IND:%.*]], [[VECTOR_BODY]] ]
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; CHECK-NEXT: [[AVL:%.*]] = phi i64 [ [[N]], [[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], [[VECTOR_BODY]] ]
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; CHECK-NEXT: [[TMP5:%.*]] = call <vscale x 2 x i64> @llvm.stepvector.nxv2i64()
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; CHECK-NEXT: [[TMP6:%.*]] = mul <vscale x 2 x i64> [[TMP5]], splat (i64 8)
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; CHECK-NEXT: [[VECTOR_GEP:%.*]] = getelementptr i8, ptr [[POINTER_PHI]], <vscale x 2 x i64> [[TMP6]]
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; CHECK-NEXT: [[TMP7:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 2, i1 true)
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; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[EVL_BASED_IV]]
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; CHECK-NEXT: call void @llvm.vp.store.nxv2p0.p0(<vscale x 2 x ptr> [[VECTOR_GEP]], ptr align 8 [[TMP8]], <vscale x 2 x i1> splat (i1 true), i32 [[TMP7]])
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; CHECK-NEXT: [[TMP9:%.*]] = zext i32 [[TMP7]] to i64
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; CHECK-NEXT: [[INDEX_EVL_NEXT]] = add i64 [[TMP9]], [[EVL_BASED_IV]]
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; CHECK-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP9]]
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; CHECK-NEXT: [[TMP10:%.*]] = zext i32 [[TMP7]] to i64
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; CHECK-NEXT: [[TMP11:%.*]] = mul i64 8, [[TMP10]]
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; CHECK-NEXT: [[PTR_IND]] = getelementptr i8, ptr [[POINTER_PHI]], i64 [[TMP11]]
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; CHECK-NEXT: [[TMP12:%.*]] = icmp eq i64 [[AVL_NEXT]], 0
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; CHECK-NEXT: br i1 [[TMP12]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
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; CHECK: middle.block:
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; CHECK-NEXT: br label [[FOR_COND_CLEANUP:%.*]]
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; CHECK: scalar.ph:
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; CHECK-NEXT: br label [[FOR_BODY:%.*]]
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; CHECK: for.body:
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; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[SCALAR_PH:%.*]] ], [ [[IV_NEXT:%.*]], [[FOR_BODY]] ]
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; CHECK-NEXT: [[ADDR:%.*]] = phi ptr [ [[INCDEC_PTR:%.*]], [[FOR_BODY]] ], [ [[B]], [[SCALAR_PH]] ]
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; CHECK-NEXT: [[INCDEC_PTR]] = getelementptr inbounds i8, ptr [[ADDR]], i64 8
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; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[IV]]
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; CHECK-NEXT: store ptr [[ADDR]], ptr [[ARRAYIDX]], align 8
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; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
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; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
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; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_COND_CLEANUP]], label [[FOR_BODY]]
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; CHECK: for.cond.cleanup:
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; CHECK-NEXT: ret void
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;
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entry:
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br label %for.body
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for.body:
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%iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
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%addr = phi ptr [ %incdec.ptr, %for.body ], [ %b, %entry ]
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%incdec.ptr = getelementptr inbounds i8, ptr %addr, i64 8
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%arrayidx = getelementptr inbounds i64, ptr %a, i64 %iv
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store ptr %addr, ptr %arrayidx, align 8
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%iv.next = add nuw nsw i64 %iv, 1
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%exitcond.not = icmp eq i64 %iv.next, %N
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br i1 %exitcond.not, label %for.cond.cleanup, label %for.body
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for.cond.cleanup:
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ret void
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}
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;.
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; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]], [[META3:![0-9]+]]}
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; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}
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; CHECK: [[META2]] = !{!"llvm.loop.isvectorized.tailfoldingstyle", !"evl"}
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; CHECK: [[META3]] = !{!"llvm.loop.unroll.runtime.disable"}
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; CHECK: [[LOOP4]] = distinct !{[[LOOP4]], [[META1]], [[META2]], [[META3]]}
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;.
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