50b9ca4dda
After https://github.com/llvm/llvm-project/pull/153643, there may be a BranchOnCond with constant condition in the entry block. Simplify those in removeBranchOnConst. This removes a number of redundant conditional branch from entry blocks. In some cases, it may also make the original scalar loop unreachable, because we know it will never execute. In that case, we need to remove the loop from LoopInfo, because all unreachable blocks may dominate each other, making LoopInfo invalid. In those cases, we can also completely remove the loop, for which I'll share a follow-up patch. Depends on https://github.com/llvm/llvm-project/pull/153643. PR: https://github.com/llvm/llvm-project/pull/154510
86 lines
4.6 KiB
LLVM
86 lines
4.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
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; RUN: opt -p loop-vectorize -force-vector-width=4 -S %s | FileCheck %s
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target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
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; Test case where the pointer index with is 32 bits, but the main IV is 64 bit.
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; Make sure VFxUF is adjusted accordingly.
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define void @wide_ptr_induction_index_width_smaller_than_iv_width(ptr noalias %src, ptr noalias %dst.0, ptr noalias %dst.1) {
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; CHECK-LABEL: define void @wide_ptr_induction_index_width_smaller_than_iv_width(
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; CHECK-SAME: ptr noalias [[SRC:%.*]], ptr noalias [[DST_0:%.*]], ptr noalias [[DST_1:%.*]]) {
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; CHECK-NEXT: [[ENTRY:.*:]]
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; CHECK-NEXT: br label %[[VECTOR_PH:.*]]
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; CHECK: [[VECTOR_PH]]:
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; CHECK-NEXT: [[TMP0:%.*]] = getelementptr i8, ptr [[SRC]], i32 800
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; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
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; CHECK: [[VECTOR_BODY]]:
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; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
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; CHECK-NEXT: [[POINTER_PHI:%.*]] = phi ptr [ [[SRC]], %[[VECTOR_PH]] ], [ [[PTR_IND:%.*]], %[[VECTOR_BODY]] ]
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; CHECK-NEXT: [[VECTOR_GEP:%.*]] = getelementptr i8, ptr [[POINTER_PHI]], <4 x i32> <i32 0, i32 8, i32 16, i32 24>
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; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[INDEX]], 0
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; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[INDEX]], 1
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; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[INDEX]], 2
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; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[INDEX]], 3
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; CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x ptr> [[VECTOR_GEP]], i32 0
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; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i64>, ptr [[TMP5]], align 1
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; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds i64, ptr [[DST_0]], i64 [[TMP1]]
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; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds i64, ptr [[DST_0]], i64 [[TMP2]]
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; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds i64, ptr [[DST_0]], i64 [[TMP3]]
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; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds i64, ptr [[DST_0]], i64 [[TMP4]]
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; CHECK-NEXT: store <4 x i64> [[WIDE_LOAD]], ptr [[TMP7]], align 8
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; CHECK-NEXT: store ptr [[TMP5]], ptr [[TMP7]], align 8
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; CHECK-NEXT: [[TMP12:%.*]] = extractelement <4 x ptr> [[VECTOR_GEP]], i32 1
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; CHECK-NEXT: store ptr [[TMP12]], ptr [[TMP8]], align 8
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; CHECK-NEXT: [[TMP13:%.*]] = extractelement <4 x ptr> [[VECTOR_GEP]], i32 2
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; CHECK-NEXT: store ptr [[TMP13]], ptr [[TMP9]], align 8
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; CHECK-NEXT: [[TMP14:%.*]] = extractelement <4 x ptr> [[VECTOR_GEP]], i32 3
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; CHECK-NEXT: store ptr [[TMP14]], ptr [[TMP10]], align 8
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; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
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; CHECK-NEXT: [[PTR_IND]] = getelementptr i8, ptr [[POINTER_PHI]], i32 32
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; CHECK-NEXT: [[TMP15:%.*]] = icmp eq i64 [[INDEX_NEXT]], 100
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; CHECK-NEXT: br i1 [[TMP15]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
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; CHECK: [[MIDDLE_BLOCK]]:
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; CHECK-NEXT: br label %[[SCALAR_PH:.*]]
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; CHECK: [[SCALAR_PH]]:
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; CHECK-NEXT: br label %[[LOOP:.*]]
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; CHECK: [[LOOP]]:
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; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 100, %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
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; CHECK-NEXT: [[PTR_IV:%.*]] = phi ptr [ [[TMP0]], %[[SCALAR_PH]] ], [ [[PTR_IV_NEXT:%.*]], %[[LOOP]] ]
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; CHECK-NEXT: [[L:%.*]] = load i64, ptr [[PTR_IV]], align 1
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; CHECK-NEXT: [[GEP_DST_1:%.*]] = getelementptr inbounds i64, ptr [[DST_0]], i64 [[IV]]
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; CHECK-NEXT: store i64 [[L]], ptr [[GEP_DST_1]], align 8
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; CHECK-NEXT: [[GEP_DST_0:%.*]] = getelementptr inbounds ptr, ptr [[DST_1]], i64 [[IV]]
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; CHECK-NEXT: store ptr [[PTR_IV]], ptr [[GEP_DST_1]], align 8
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; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
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; CHECK-NEXT: [[PTR_IV_NEXT]] = getelementptr i8, ptr [[PTR_IV]], i32 8
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; CHECK-NEXT: [[EC:%.*]] = icmp ult i64 [[IV]], 100
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; CHECK-NEXT: br i1 [[EC]], label %[[LOOP]], label %[[EXIT:.*]], !llvm.loop [[LOOP3:![0-9]+]]
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; CHECK: [[EXIT]]:
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; CHECK-NEXT: ret void
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;
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entry:
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br label %loop
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loop:
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%iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
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%ptr.iv = phi ptr [ %src, %entry ], [ %ptr.iv.next, %loop ]
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%l = load i64, ptr %ptr.iv, align 1
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%gep.dst.1 = getelementptr inbounds i64, ptr %dst.0, i64 %iv
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store i64 %l, ptr %gep.dst.1, align 8
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%gep.dst.0 = getelementptr inbounds ptr, ptr %dst.1, i64 %iv
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store ptr %ptr.iv, ptr %gep.dst.1, align 8
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%iv.next = add i64 %iv, 1
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%ptr.iv.next = getelementptr i8, ptr %ptr.iv, i32 8
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%ec = icmp ult i64 %iv, 100
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br i1 %ec, label %loop, label %exit
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exit:
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ret void
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}
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;.
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; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}
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; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}
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; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}
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; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META2]], [[META1]]}
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;.
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