50b9ca4dda
After https://github.com/llvm/llvm-project/pull/153643, there may be a BranchOnCond with constant condition in the entry block. Simplify those in removeBranchOnConst. This removes a number of redundant conditional branch from entry blocks. In some cases, it may also make the original scalar loop unreachable, because we know it will never execute. In that case, we need to remove the loop from LoopInfo, because all unreachable blocks may dominate each other, making LoopInfo invalid. In those cases, we can also completely remove the loop, for which I'll share a follow-up patch. Depends on https://github.com/llvm/llvm-project/pull/153643. PR: https://github.com/llvm/llvm-project/pull/154510
92 lines
4.3 KiB
LLVM
92 lines
4.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 3
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; RUN: opt -passes="print<scalar-evolution>,loop-vectorize" --verify-scev -S < %s -force-vector-width=4 2>/dev/null | FileCheck %s
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; Make sure users of SCEVUnknowns from the scalar loop are invalidated.
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define void @pr66616(ptr %ptr) {
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; CHECK-LABEL: define void @pr66616(
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; CHECK-SAME: ptr [[PTR:%.*]]) {
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[VECTOR_PH:%.*]]
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; CHECK: vector.ph:
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; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
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; CHECK: vector.body:
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; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
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; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[PTR]], align 4
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; CHECK-NEXT: [[TMP3:%.*]] = add i32 [[TMP0]], 1
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; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4
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; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32 [[INDEX_NEXT]], 256
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; CHECK-NEXT: br i1 [[TMP2]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
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; CHECK: middle.block:
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; CHECK-NEXT: br label [[PREHEADER:%.*]]
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; CHECK: scalar.ph:
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; CHECK-NEXT: br label [[LOOP_1:%.*]]
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; CHECK: loop.1:
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; CHECK-NEXT: [[IV_1:%.*]] = phi i8 [ 0, [[SCALAR_PH:%.*]] ], [ [[INC:%.*]], [[LOOP_1]] ]
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; CHECK-NEXT: [[LOAD:%.*]] = load i32, ptr [[PTR]], align 4
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; CHECK-NEXT: [[ADD3:%.*]] = add i32 [[LOAD]], 1
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; CHECK-NEXT: [[INC]] = add i8 [[IV_1]], 1
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; CHECK-NEXT: [[COND1:%.*]] = icmp eq i8 [[INC]], 0
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; CHECK-NEXT: br i1 [[COND1]], label [[PREHEADER]], label [[LOOP_1]]
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; CHECK: preheader:
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; CHECK-NEXT: [[ADD3_LCSSA:%.*]] = phi i32 [ [[ADD3]], [[LOOP_1]] ], [ [[TMP3]], [[MIDDLE_BLOCK]] ]
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; CHECK-NEXT: [[TMP4:%.*]] = sub i32 0, [[ADD3_LCSSA]]
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; CHECK-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64
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; CHECK-NEXT: [[TMP6:%.*]] = add nuw nsw i64 [[TMP5]], 1
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; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP6]], 4
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; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH1:%.*]], label [[VECTOR_PH2:%.*]]
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; CHECK: vector.ph2:
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; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP6]], 4
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; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP6]], [[N_MOD_VF]]
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; CHECK-NEXT: [[DOTCAST:%.*]] = trunc i64 [[N_VEC]] to i32
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; CHECK-NEXT: [[IND_END:%.*]] = add i32 [[ADD3_LCSSA]], [[DOTCAST]]
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; CHECK-NEXT: [[IND_END5:%.*]] = getelementptr i8, ptr [[PTR]], i64 [[N_VEC]]
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; CHECK-NEXT: br label [[VECTOR_BODY3:%.*]]
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; CHECK: vector.body3:
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; CHECK-NEXT: [[INDEX8:%.*]] = phi i64 [ 0, [[VECTOR_PH2]] ], [ [[INDEX_NEXT9:%.*]], [[VECTOR_BODY3]] ]
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; CHECK-NEXT: [[INDEX_NEXT9]] = add nuw i64 [[INDEX8]], 4
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; CHECK-NEXT: [[TMP7:%.*]] = icmp eq i64 [[INDEX_NEXT9]], [[N_VEC]]
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; CHECK-NEXT: br i1 [[TMP7]], label [[MIDDLE_BLOCK6:%.*]], label [[VECTOR_BODY3]], !llvm.loop [[LOOP3:![0-9]+]]
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; CHECK: middle.block6:
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; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP6]], [[N_VEC]]
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; CHECK-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[SCALAR_PH1]]
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; CHECK: scalar.ph1:
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; CHECK-NEXT: [[BC_RESUME_VAL4:%.*]] = phi i32 [ [[IND_END]], [[MIDDLE_BLOCK6]] ], [ [[ADD3_LCSSA]], [[PREHEADER]] ]
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; CHECK-NEXT: [[BC_RESUME_VAL6:%.*]] = phi ptr [ [[IND_END5]], [[MIDDLE_BLOCK6]] ], [ [[PTR]], [[PREHEADER]] ]
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; CHECK-NEXT: br label [[LOOP_2:%.*]]
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; CHECK: loop.2:
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; CHECK-NEXT: [[IV_2:%.*]] = phi i32 [ [[IV_2_I:%.*]], [[LOOP_2]] ], [ [[BC_RESUME_VAL4]], [[SCALAR_PH1]] ]
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; CHECK-NEXT: [[IV_3:%.*]] = phi ptr [ [[IV_3_I:%.*]], [[LOOP_2]] ], [ [[BC_RESUME_VAL6]], [[SCALAR_PH1]] ]
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; CHECK-NEXT: [[IV_2_I]] = add i32 [[IV_2]], 1
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; CHECK-NEXT: [[IV_3_I]] = getelementptr i8, ptr [[IV_3]], i64 1
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; CHECK-NEXT: [[COND2:%.*]] = icmp eq i32 [[IV_2]], 0
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; CHECK-NEXT: br i1 [[COND2]], label [[EXIT]], label [[LOOP_2]], !llvm.loop [[LOOP4:![0-9]+]]
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; CHECK: exit:
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; CHECK-NEXT: ret void
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;
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entry:
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br label %loop.1
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loop.1:
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%iv.1 = phi i8 [ 0, %entry ], [ %inc, %loop.1 ]
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%load = load i32, ptr %ptr, align 4
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%add3 = add i32 %load, 1
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%inc = add i8 %iv.1, 1
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%cond1 = icmp eq i8 %inc, 0
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br i1 %cond1, label %preheader, label %loop.1
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preheader:
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br label %loop.2
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loop.2:
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%iv.2 = phi i32 [ %iv.2.i, %loop.2 ], [ %add3, %preheader ]
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%iv.3 = phi ptr [ %iv.3.i, %loop.2 ], [ %ptr, %preheader ]
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%iv.2.i = add i32 %iv.2, 1
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%iv.3.i = getelementptr i8, ptr %iv.3, i64 1
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%cond2 = icmp eq i32 %iv.2, 0
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br i1 %cond2, label %exit, label %loop.2
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exit:
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ret void
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}
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