50b9ca4dda
After https://github.com/llvm/llvm-project/pull/153643, there may be a BranchOnCond with constant condition in the entry block. Simplify those in removeBranchOnConst. This removes a number of redundant conditional branch from entry blocks. In some cases, it may also make the original scalar loop unreachable, because we know it will never execute. In that case, we need to remove the loop from LoopInfo, because all unreachable blocks may dominate each other, making LoopInfo invalid. In those cases, we can also completely remove the loop, for which I'll share a follow-up patch. Depends on https://github.com/llvm/llvm-project/pull/153643. PR: https://github.com/llvm/llvm-project/pull/154510
105 lines
5.1 KiB
LLVM
105 lines
5.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
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; RUN: opt -p loop-vectorize -force-vector-width=4 -force-vector-interleave=1 -prefer-predicate-over-epilogue=predicate-dont-vectorize -S %s | FileCheck %s
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target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128-Fn32"
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define void @tail_fold_switch(ptr %dst, i32 %0) {
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; CHECK-LABEL: define void @tail_fold_switch(
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; CHECK-SAME: ptr [[DST:%.*]], i32 [[TMP0:%.*]]) {
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; CHECK-NEXT: [[ENTRY:.*:]]
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; CHECK-NEXT: br label %[[VECTOR_PH:.*]]
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; CHECK: [[VECTOR_PH]]:
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; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i32> poison, i32 [[TMP0]], i64 0
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; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT]], <4 x i32> poison, <4 x i32> zeroinitializer
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; CHECK-NEXT: [[TMP2:%.*]] = icmp eq <4 x i32> [[BROADCAST_SPLAT]], splat (i32 1)
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; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
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; CHECK: [[VECTOR_BODY]]:
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; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_STORE_CONTINUE6:.*]] ]
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; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i8> [ <i8 0, i8 1, i8 2, i8 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[PRED_STORE_CONTINUE6]] ]
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; CHECK-NEXT: [[TMP1:%.*]] = icmp ule <4 x i8> [[VEC_IND]], splat (i8 4)
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; CHECK-NEXT: [[TMP3:%.*]] = select <4 x i1> [[TMP1]], <4 x i1> [[TMP2]], <4 x i1> zeroinitializer
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; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x i1> [[TMP3]], i32 0
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; CHECK-NEXT: br i1 [[TMP4]], label %[[PRED_STORE_IF:.*]], label %[[PRED_STORE_CONTINUE:.*]]
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; CHECK: [[PRED_STORE_IF]]:
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; CHECK-NEXT: [[TMP5:%.*]] = add i64 [[INDEX]], 0
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; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[DST]], i64 [[TMP5]]
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; CHECK-NEXT: store i32 0, ptr [[TMP6]], align 4
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; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE]]
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; CHECK: [[PRED_STORE_CONTINUE]]:
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; CHECK-NEXT: [[TMP7:%.*]] = extractelement <4 x i1> [[TMP3]], i32 1
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; CHECK-NEXT: br i1 [[TMP7]], label %[[PRED_STORE_IF1:.*]], label %[[PRED_STORE_CONTINUE2:.*]]
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; CHECK: [[PRED_STORE_IF1]]:
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; CHECK-NEXT: [[TMP8:%.*]] = add i64 [[INDEX]], 1
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; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds i32, ptr [[DST]], i64 [[TMP8]]
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; CHECK-NEXT: store i32 0, ptr [[TMP9]], align 4
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; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE2]]
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; CHECK: [[PRED_STORE_CONTINUE2]]:
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; CHECK-NEXT: [[TMP10:%.*]] = extractelement <4 x i1> [[TMP3]], i32 2
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; CHECK-NEXT: br i1 [[TMP10]], label %[[PRED_STORE_IF3:.*]], label %[[PRED_STORE_CONTINUE4:.*]]
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; CHECK: [[PRED_STORE_IF3]]:
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; CHECK-NEXT: [[TMP11:%.*]] = add i64 [[INDEX]], 2
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; CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds i32, ptr [[DST]], i64 [[TMP11]]
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; CHECK-NEXT: store i32 0, ptr [[TMP12]], align 4
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; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE4]]
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; CHECK: [[PRED_STORE_CONTINUE4]]:
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; CHECK-NEXT: [[TMP13:%.*]] = extractelement <4 x i1> [[TMP3]], i32 3
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; CHECK-NEXT: br i1 [[TMP13]], label %[[PRED_STORE_IF5:.*]], label %[[PRED_STORE_CONTINUE6]]
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; CHECK: [[PRED_STORE_IF5]]:
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; CHECK-NEXT: [[TMP14:%.*]] = add i64 [[INDEX]], 3
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; CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds i32, ptr [[DST]], i64 [[TMP14]]
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; CHECK-NEXT: store i32 0, ptr [[TMP15]], align 4
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; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE6]]
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; CHECK: [[PRED_STORE_CONTINUE6]]:
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; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
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; CHECK-NEXT: [[VEC_IND_NEXT]] = add <4 x i8> [[VEC_IND]], splat (i8 4)
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; CHECK-NEXT: [[TMP16:%.*]] = icmp eq i64 [[INDEX_NEXT]], 8
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; CHECK-NEXT: br i1 [[TMP16]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
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; CHECK: [[MIDDLE_BLOCK]]:
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; CHECK-NEXT: br label %[[EXIT:.*]]
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; CHECK: [[SCALAR_PH:.*]]:
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; CHECK-NEXT: br label %[[LOOP_HEADER:.*]]
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; CHECK: [[LOOP_HEADER]]:
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; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ]
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; CHECK-NEXT: switch i32 [[TMP0]], label %[[LOOP_LATCH]] [
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; CHECK-NEXT: i32 0, label %[[LOOP_LATCH]]
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; CHECK-NEXT: i32 1, label %[[IF_THEN:.*]]
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; CHECK-NEXT: ]
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; CHECK: [[IF_THEN]]:
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; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds i32, ptr [[DST]], i64 [[IV]]
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; CHECK-NEXT: store i32 0, ptr [[GEP]], align 4
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; CHECK-NEXT: br label %[[LOOP_LATCH]]
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; CHECK: [[LOOP_LATCH]]:
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; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
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; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV]], 4
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; CHECK-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP_HEADER]]
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; CHECK: [[EXIT]]:
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; CHECK-NEXT: ret void
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;
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entry:
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br label %loop.header
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loop.header:
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%iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ]
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switch i32 %0, label %loop.latch [
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i32 0, label %loop.latch
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i32 1, label %if.then
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]
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if.then:
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%gep = getelementptr inbounds i32, ptr %dst, i64 %iv
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store i32 0, ptr %gep, align 4
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br label %loop.latch
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loop.latch:
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%iv.next = add i64 %iv, 1
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%ec = icmp eq i64 %iv, 4
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br i1 %ec, label %exit, label %loop.header
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exit:
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ret void
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}
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;.
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; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}
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; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}
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; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}
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;.
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