Gaurav Verma a2a9601ea4

[mlir][AMDGPU] Updated PermlaneSwapOp to select correct val (#157586) ...

* as per the instruction description, updated `PermlaneSwapOp` to select
correct val
* updated corresponding lit tests

Issue it resolves: the block reduction was failing otherwise as we were
selecting the `{0}` always.

---------

Signed-off-by: xintin <gaurav.verma@amd.com>

2025-09-12 13:45:56 +02:00

..

8-bit-floats-ocp.mlir

[mlir][ROCDL] Add fp4 and fp6 conversion intrinsics, fix fp8 immargs (#140801)

2025-05-21 13:50:02 -07:00

8-bit-floats.mlir

[mlir][ROCDL] Add fp4 and fp6 conversion intrinsics, fix fp8 immargs (#140801)

2025-05-21 13:50:02 -07:00

amdgpu-to-rocdl.mlir

[mlir][AMDGPU] Infer canonical layouts for fat_raw_buffer_cast resetOffset (#149867)

2025-07-21 15:18:19 -05:00

dpp.mlir

[mlir][AMDGPU] Implement AMDGPU DPP operation in MLIR. (#89233)

2024-08-16 11:19:39 -05:00

load_lds-gfx950.mlir

[AMDGPU] [MLIR] Add 96 and 128 bit GatherToLDS for gfx950 (#147496)

2025-07-09 11:53:26 -04:00

load_lds.mlir

[mlir][amdgpu] Properly handle mismatching memref ranks in amdgpu.gather_to_lds (#149407)

2025-07-18 00:42:25 +03:00

memory_counter_wait.mlir

[mlir][amdgpu] Add rocdl.s.waitcnt wrapper (#149670)

2025-07-22 23:37:56 +03:00

mfma-gfx950.mlir

Allow bf16 operands on new MFMAs (#144925)

2025-06-19 12:52:31 -05:00

mfma.mlir

[AMDGPU][MLIR] Replace gfx940 and gfx941 with gfx942 in MLIR (#125836)

2025-02-19 10:05:45 +01:00

packed-ext.mlir

[mlir][AMDGPU] Add scaled floating point conversion ops (#141554)

2025-06-13 11:09:11 +02:00

packed-trunc.mlir

[mlir][AMDGPU] Add scaled floating point conversion ops (#141554)

2025-06-13 11:09:11 +02:00

permlane.mlir

[mlir][AMDGPU] Updated PermlaneSwapOp to select correct val (#157586)

2025-09-12 13:45:56 +02:00

swizzle.mlir

[mlir] AMDGPUToROCDL: lower amdgpu.swizzle_bitmode (#136223)

2025-04-18 17:19:04 +03:00

transpose_load_reject.mlir

[AMDGPU] Adding AMDGPU dialect wrapper for ROCDL transpose loads. (#145395)

2025-06-25 22:58:14 -04:00

transpose_load.mlir

[AMDGPU] [MLIR] Add 96 and 128 bit GatherToLDS for gfx950 (#147496)

2025-07-09 11:53:26 -04:00

wmma-gfx12.mlir

[mlir][AMDGPU] Add int4 intrinsics, mixed-type fp8 to handle gfx12 (#128963)

2025-02-27 14:48:58 -06:00

wmma.mlir

[mlir][AMDGPU] Add int4 intrinsics, mixed-type fp8 to handle gfx12 (#128963)

2025-02-27 14:48:58 -06:00