796ed6d937
Summary: This commit resolves wrong opcodes for ll and sc instructions for r6 architecutres, which were generated in method MipsTargetLowering::emitAtomicBinary. Author: Jelena.Losic Reviewers: dsanders Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D13593 llvm-svn: 251629
33 lines
938 B
LLVM
33 lines
938 B
LLVM
; RUN: llc -asm-show-inst -march=mips64el -mcpu=mips64r6 < %s -filetype=asm -o - | FileCheck %s -check-prefix=CHK64
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; RUN: llc -asm-show-inst -march=mipsel -mcpu=mips32r6 < %s -filetype=asm -o -| FileCheck %s -check-prefix=CHK32
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define internal i32 @atomic_load_test1() #0 {
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entry:
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%load_add = alloca i32*, align 8
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%.atomicdst = alloca i32, align 4
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%0 = load i32*, i32** %load_add, align 8
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%1 = load atomic i32, i32* %0 acquire, align 4
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store i32 %1, i32* %.atomicdst, align 4
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%2 = load i32, i32* %.atomicdst, align 4
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ret i32 %2
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}
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define internal i64 @atomic_load_test2() #0 {
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entry:
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%load_add = alloca i64*, align 16
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%.atomicdst = alloca i64, align 8
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%0 = load i64*, i64** %load_add, align 16
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%1 = load atomic i64, i64* %0 acquire, align 8
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store i64 %1, i64* %.atomicdst, align 8
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%2 = load i64, i64* %.atomicdst, align 8
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ret i64 %2
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}
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;CHK32: LL_R6
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;CHK32: SC_R6
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;CHK64: LLD_R6
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;CHK64: SCD_R6
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