f4ee371e60
These flags are now always passed to all tests and need to be disabled if not needed. Disabling these flags, rather than passing them to almost all tests, significantly simplfies our RUN: lines. llvm-svn: 249422
107 lines
4.8 KiB
LLVM
107 lines
4.8 KiB
LLVM
; RUN: opt -S %loadPolly -basicaa -polly-opt-isl -polly-vectorizer=polly -polly-ast -analyze < %s | FileCheck %s
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; RUN: opt -S %loadPolly -basicaa -polly-opt-isl -polly-vectorizer=stripmine -polly-ast -analyze < %s | FileCheck %s
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; RUN: opt -S %loadPolly -basicaa -polly-opt-isl \
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; RUN: -polly-vectorizer=polly -polly-ast -analyze \
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; RUN: -polly-prevect-width=16 < %s | \
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; RUN: FileCheck %s -check-prefix=VEC16
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target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
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@C = common global [1536 x [1536 x float]] zeroinitializer, align 16
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@A = common global [1536 x [1536 x float]] zeroinitializer, align 16
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@B = common global [1536 x [1536 x float]] zeroinitializer, align 16
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; Function Attrs: nounwind uwtable
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define void @foo() #0 {
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entry:
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br label %entry.split
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entry.split: ; preds = %entry
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br label %for.cond1.preheader
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for.cond1.preheader: ; preds = %entry.split, %for.inc28
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%indvar4 = phi i64 [ 0, %entry.split ], [ %indvar.next5, %for.inc28 ]
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br label %for.body3
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for.body3: ; preds = %for.cond1.preheader, %for.inc25
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%indvar6 = phi i64 [ 0, %for.cond1.preheader ], [ %indvar.next7, %for.inc25 ]
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%arrayidx24 = getelementptr [1536 x [1536 x float]], [1536 x [1536 x float]]* @C, i64 0, i64 %indvar4, i64 %indvar6
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store float 0.000000e+00, float* %arrayidx24, align 4
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br label %for.body8
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for.body8: ; preds = %for.body3, %for.body8
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%indvar = phi i64 [ 0, %for.body3 ], [ %indvar.next, %for.body8 ]
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%arrayidx16 = getelementptr [1536 x [1536 x float]], [1536 x [1536 x float]]* @A, i64 0, i64 %indvar4, i64 %indvar
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%arrayidx20 = getelementptr [1536 x [1536 x float]], [1536 x [1536 x float]]* @B, i64 0, i64 %indvar, i64 %indvar6
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%0 = load float, float* %arrayidx24, align 4
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%1 = load float, float* %arrayidx16, align 4
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%2 = load float, float* %arrayidx20, align 4
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%mul = fmul float %1, %2
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%add = fadd float %0, %mul
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store float %add, float* %arrayidx24, align 4
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%indvar.next = add i64 %indvar, 1
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%exitcond = icmp ne i64 %indvar.next, 1536
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br i1 %exitcond, label %for.body8, label %for.inc25
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for.inc25: ; preds = %for.body8
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%indvar.next7 = add i64 %indvar6, 1
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%exitcond8 = icmp ne i64 %indvar.next7, 1536
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br i1 %exitcond8, label %for.body3, label %for.inc28
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for.inc28: ; preds = %for.inc25
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%indvar.next5 = add i64 %indvar4, 1
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%exitcond9 = icmp ne i64 %indvar.next5, 1536
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br i1 %exitcond9, label %for.cond1.preheader, label %for.end30
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for.end30: ; preds = %for.inc28
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ret void
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}
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attributes #0 = { nounwind uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
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; CHECK: #pragma known-parallel
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; CHECK: for (int c0 = 0; c0 <= 47; c0 += 1)
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; CHECK: for (int c1 = 0; c1 <= 47; c1 += 1)
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; CHECK: for (int c2 = 0; c2 <= 31; c2 += 1)
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; CHECK: for (int c3 = 0; c3 <= 7; c3 += 1)
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; CHECK: #pragma simd
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; CHECK: for (int c4 = 0; c4 <= 3; c4 += 1)
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; CHECK: Stmt_for_body3(32 * c0 + c2, 32 * c1 + 4 * c3 + c4);
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; CHECK: #pragma known-parallel
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; CHECK: for (int c0 = 0; c0 <= 47; c0 += 1)
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; CHECK: for (int c1 = 0; c1 <= 47; c1 += 1)
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; CHECK: for (int c2 = 0; c2 <= 47; c2 += 1)
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; CHECK: for (int c3 = 0; c3 <= 31; c3 += 1)
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; CHECK: for (int c4 = 0; c4 <= 7; c4 += 1)
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; CHECK: for (int c5 = 0; c5 <= 31; c5 += 1)
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; CHECK: #pragma simd
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; CHECK: for (int c6 = 0; c6 <= 3; c6 += 1)
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; CHECK: Stmt_for_body8(32 * c0 + c3, 32 * c1 + 4 * c4 + c6, 32 * c2 + c5);
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; VEC16: {
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; VEC16: #pragma known-parallel
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; VEC16: for (int c0 = 0; c0 <= 47; c0 += 1)
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; VEC16: for (int c1 = 0; c1 <= 47; c1 += 1)
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; VEC16: for (int c2 = 0; c2 <= 31; c2 += 1)
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; VEC16: for (int c3 = 0; c3 <= 1; c3 += 1)
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; VEC16: #pragma simd
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; VEC16: for (int c4 = 0; c4 <= 15; c4 += 1)
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; VEC16: Stmt_for_body3(32 * c0 + c2, 32 * c1 + 16 * c3 + c4);
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; VEC16: #pragma known-parallel
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; VEC16: for (int c0 = 0; c0 <= 47; c0 += 1)
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; VEC16: for (int c1 = 0; c1 <= 47; c1 += 1)
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; VEC16: for (int c2 = 0; c2 <= 47; c2 += 1)
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; VEC16: for (int c3 = 0; c3 <= 31; c3 += 1)
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; VEC16: for (int c4 = 0; c4 <= 1; c4 += 1)
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; VEC16: for (int c5 = 0; c5 <= 31; c5 += 1)
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; VEC16: #pragma simd
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; VEC16: for (int c6 = 0; c6 <= 15; c6 += 1)
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; VEC16: Stmt_for_body8(32 * c0 + c3, 32 * c1 + 16 * c4 + c6, 32 * c2 + c5);
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; VEC16: }
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!llvm.ident = !{!0}
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!0 = !{!"clang version 3.5.0 "}
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