cc19f420b9
Port AMDGPUArgumentUsageInfo analysis to the NPM to fix suboptimal code generation when NPM is enabled by default. Previously, DAG.getPass() returns nullptr when using NPM, causing the argument usage info to be unavailable during ISel. This resulted in fallback to FixedABIFunctionInfo which assumes all implicit arguments are needed, generating unnecessary register setup code for entry functions. Fixes LLVM::CodeGen/AMDGPU/cc-entry.ll Changes: - Split AMDGPUArgumentUsageInfo into a data class and NPM analysis wrapper - Update SIISelLowering to use DAG.getMFAM() for NPM path - Add RequireAnalysisPass in addPreISel() to ensure analysis availability This follows the same pattern used for PhysicalRegisterUsageInfo.
198 lines
8.5 KiB
C++
198 lines
8.5 KiB
C++
//===----------------------------------------------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "AMDGPUArgumentUsageInfo.h"
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#include "AMDGPU.h"
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#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
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#include "SIRegisterInfo.h"
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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#include "llvm/IR/Function.h"
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#include "llvm/Support/NativeFormatting.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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#define DEBUG_TYPE "amdgpu-argument-reg-usage-info"
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INITIALIZE_PASS(AMDGPUArgumentUsageInfoWrapperLegacy, DEBUG_TYPE,
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"Argument Register Usage Information Storage", false, true)
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void ArgDescriptor::print(raw_ostream &OS,
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const TargetRegisterInfo *TRI) const {
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if (!isSet()) {
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OS << "<not set>\n";
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return;
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}
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if (isRegister())
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OS << "Reg " << printReg(getRegister(), TRI);
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else
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OS << "Stack offset " << getStackOffset();
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if (isMasked()) {
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OS << " & ";
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llvm::write_hex(OS, Mask, llvm::HexPrintStyle::PrefixLower);
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}
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OS << '\n';
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}
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char AMDGPUArgumentUsageInfoWrapperLegacy::ID = 0;
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const AMDGPUFunctionArgInfo AMDGPUArgumentUsageInfo::ExternFunctionInfo{};
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// Hardcoded registers from fixed function ABI
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const AMDGPUFunctionArgInfo AMDGPUArgumentUsageInfo::FixedABIFunctionInfo
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= AMDGPUFunctionArgInfo::fixedABILayout();
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// TODO: Print preload kernargs?
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void AMDGPUArgumentUsageInfo::print(raw_ostream &OS, const Module *M) const {
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for (const auto &FI : ArgInfoMap) {
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OS << "Arguments for " << FI.first->getName() << '\n'
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<< " PrivateSegmentBuffer: " << FI.second.PrivateSegmentBuffer
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<< " DispatchPtr: " << FI.second.DispatchPtr
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<< " QueuePtr: " << FI.second.QueuePtr
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<< " KernargSegmentPtr: " << FI.second.KernargSegmentPtr
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<< " DispatchID: " << FI.second.DispatchID
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<< " FlatScratchInit: " << FI.second.FlatScratchInit
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<< " PrivateSegmentSize: " << FI.second.PrivateSegmentSize
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<< " WorkGroupIDX: " << FI.second.WorkGroupIDX
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<< " WorkGroupIDY: " << FI.second.WorkGroupIDY
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<< " WorkGroupIDZ: " << FI.second.WorkGroupIDZ
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<< " WorkGroupInfo: " << FI.second.WorkGroupInfo
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<< " LDSKernelId: " << FI.second.LDSKernelId
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<< " PrivateSegmentWaveByteOffset: "
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<< FI.second.PrivateSegmentWaveByteOffset
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<< " ImplicitBufferPtr: " << FI.second.ImplicitBufferPtr
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<< " ImplicitArgPtr: " << FI.second.ImplicitArgPtr
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<< " WorkItemIDX " << FI.second.WorkItemIDX
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<< " WorkItemIDY " << FI.second.WorkItemIDY
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<< " WorkItemIDZ " << FI.second.WorkItemIDZ
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<< '\n';
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}
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}
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bool AMDGPUArgumentUsageInfo::invalidate(Module &M, const PreservedAnalyses &PA,
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ModuleAnalysisManager::Invalidator &) {
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auto PAC = PA.getChecker<AMDGPUArgumentUsageAnalysis>();
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return !PAC.preservedWhenStateless();
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}
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std::tuple<const ArgDescriptor *, const TargetRegisterClass *, LLT>
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AMDGPUFunctionArgInfo::getPreloadedValue(
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AMDGPUFunctionArgInfo::PreloadedValue Value) const {
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switch (Value) {
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case AMDGPUFunctionArgInfo::PRIVATE_SEGMENT_BUFFER: {
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return std::tuple(PrivateSegmentBuffer ? &PrivateSegmentBuffer : nullptr,
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&AMDGPU::SGPR_128RegClass, LLT::fixed_vector(4, 32));
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}
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case AMDGPUFunctionArgInfo::IMPLICIT_BUFFER_PTR:
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return std::tuple(ImplicitBufferPtr ? &ImplicitBufferPtr : nullptr,
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&AMDGPU::SGPR_64RegClass,
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LLT::pointer(AMDGPUAS::CONSTANT_ADDRESS, 64));
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case AMDGPUFunctionArgInfo::WORKGROUP_ID_X:
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return std::tuple(WorkGroupIDX ? &WorkGroupIDX : nullptr,
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&AMDGPU::SGPR_32RegClass, LLT::scalar(32));
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case AMDGPUFunctionArgInfo::WORKGROUP_ID_Y:
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return std::tuple(WorkGroupIDY ? &WorkGroupIDY : nullptr,
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&AMDGPU::SGPR_32RegClass, LLT::scalar(32));
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case AMDGPUFunctionArgInfo::WORKGROUP_ID_Z:
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return std::tuple(WorkGroupIDZ ? &WorkGroupIDZ : nullptr,
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&AMDGPU::SGPR_32RegClass, LLT::scalar(32));
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case AMDGPUFunctionArgInfo::CLUSTER_WORKGROUP_ID_X:
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case AMDGPUFunctionArgInfo::CLUSTER_WORKGROUP_ID_Y:
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case AMDGPUFunctionArgInfo::CLUSTER_WORKGROUP_ID_Z:
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case AMDGPUFunctionArgInfo::CLUSTER_WORKGROUP_MAX_ID_X:
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case AMDGPUFunctionArgInfo::CLUSTER_WORKGROUP_MAX_ID_Y:
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case AMDGPUFunctionArgInfo::CLUSTER_WORKGROUP_MAX_ID_Z:
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case AMDGPUFunctionArgInfo::CLUSTER_WORKGROUP_MAX_FLAT_ID:
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return std::tuple(nullptr, &AMDGPU::SGPR_32RegClass, LLT::scalar(32));
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case AMDGPUFunctionArgInfo::LDS_KERNEL_ID:
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return std::tuple(LDSKernelId ? &LDSKernelId : nullptr,
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&AMDGPU::SGPR_32RegClass, LLT::scalar(32));
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case AMDGPUFunctionArgInfo::PRIVATE_SEGMENT_WAVE_BYTE_OFFSET:
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return std::tuple(
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PrivateSegmentWaveByteOffset ? &PrivateSegmentWaveByteOffset : nullptr,
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&AMDGPU::SGPR_32RegClass, LLT::scalar(32));
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case AMDGPUFunctionArgInfo::PRIVATE_SEGMENT_SIZE:
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return {PrivateSegmentSize ? &PrivateSegmentSize : nullptr,
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&AMDGPU::SGPR_32RegClass, LLT::scalar(32)};
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case AMDGPUFunctionArgInfo::KERNARG_SEGMENT_PTR:
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return std::tuple(KernargSegmentPtr ? &KernargSegmentPtr : nullptr,
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&AMDGPU::SGPR_64RegClass,
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LLT::pointer(AMDGPUAS::CONSTANT_ADDRESS, 64));
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case AMDGPUFunctionArgInfo::IMPLICIT_ARG_PTR:
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return std::tuple(ImplicitArgPtr ? &ImplicitArgPtr : nullptr,
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&AMDGPU::SGPR_64RegClass,
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LLT::pointer(AMDGPUAS::CONSTANT_ADDRESS, 64));
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case AMDGPUFunctionArgInfo::DISPATCH_ID:
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return std::tuple(DispatchID ? &DispatchID : nullptr,
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&AMDGPU::SGPR_64RegClass, LLT::scalar(64));
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case AMDGPUFunctionArgInfo::FLAT_SCRATCH_INIT:
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return std::tuple(FlatScratchInit ? &FlatScratchInit : nullptr,
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&AMDGPU::SGPR_64RegClass, LLT::scalar(64));
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case AMDGPUFunctionArgInfo::DISPATCH_PTR:
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return std::tuple(DispatchPtr ? &DispatchPtr : nullptr,
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&AMDGPU::SGPR_64RegClass,
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LLT::pointer(AMDGPUAS::CONSTANT_ADDRESS, 64));
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case AMDGPUFunctionArgInfo::QUEUE_PTR:
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return std::tuple(QueuePtr ? &QueuePtr : nullptr, &AMDGPU::SGPR_64RegClass,
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LLT::pointer(AMDGPUAS::CONSTANT_ADDRESS, 64));
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case AMDGPUFunctionArgInfo::WORKITEM_ID_X:
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return std::tuple(WorkItemIDX ? &WorkItemIDX : nullptr,
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&AMDGPU::VGPR_32RegClass, LLT::scalar(32));
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case AMDGPUFunctionArgInfo::WORKITEM_ID_Y:
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return std::tuple(WorkItemIDY ? &WorkItemIDY : nullptr,
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&AMDGPU::VGPR_32RegClass, LLT::scalar(32));
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case AMDGPUFunctionArgInfo::WORKITEM_ID_Z:
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return std::tuple(WorkItemIDZ ? &WorkItemIDZ : nullptr,
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&AMDGPU::VGPR_32RegClass, LLT::scalar(32));
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}
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llvm_unreachable("unexpected preloaded value type");
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}
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AMDGPUFunctionArgInfo AMDGPUFunctionArgInfo::fixedABILayout() {
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AMDGPUFunctionArgInfo AI;
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AI.PrivateSegmentBuffer
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= ArgDescriptor::createRegister(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3);
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AI.DispatchPtr = ArgDescriptor::createRegister(AMDGPU::SGPR4_SGPR5);
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AI.QueuePtr = ArgDescriptor::createRegister(AMDGPU::SGPR6_SGPR7);
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// Do not pass kernarg segment pointer, only pass increment version in its
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// place.
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AI.ImplicitArgPtr = ArgDescriptor::createRegister(AMDGPU::SGPR8_SGPR9);
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AI.DispatchID = ArgDescriptor::createRegister(AMDGPU::SGPR10_SGPR11);
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// Skip FlatScratchInit/PrivateSegmentSize
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AI.WorkGroupIDX = ArgDescriptor::createRegister(AMDGPU::SGPR12);
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AI.WorkGroupIDY = ArgDescriptor::createRegister(AMDGPU::SGPR13);
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AI.WorkGroupIDZ = ArgDescriptor::createRegister(AMDGPU::SGPR14);
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AI.LDSKernelId = ArgDescriptor::createRegister(AMDGPU::SGPR15);
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const unsigned Mask = 0x3ff;
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AI.WorkItemIDX = ArgDescriptor::createRegister(AMDGPU::VGPR31, Mask);
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AI.WorkItemIDY = ArgDescriptor::createRegister(AMDGPU::VGPR31, Mask << 10);
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AI.WorkItemIDZ = ArgDescriptor::createRegister(AMDGPU::VGPR31, Mask << 20);
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return AI;
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}
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const AMDGPUFunctionArgInfo &
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AMDGPUArgumentUsageInfo::lookupFuncArgInfo(const Function &F) const {
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auto I = ArgInfoMap.find(&F);
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if (I == ArgInfoMap.end())
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return FixedABIFunctionInfo;
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return I->second;
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}
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AnalysisKey AMDGPUArgumentUsageAnalysis::Key;
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AMDGPUArgumentUsageInfo
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AMDGPUArgumentUsageAnalysis::run(Module &M, ModuleAnalysisManager &) {
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return AMDGPUArgumentUsageInfo();
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}
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