adec922361
We would like to start pushing -mcpu=generic towards enabling the set of features that improves performance for some CPUs, without hurting any others. A blend of the performance options hopefully beneficial to all CPUs. The largest part of that is enabling in-order scheduling using the Cortex-A55 schedule model. This is similar to the Arm backend change from eecb353d0e25ba which made -mcpu=generic perform in-order scheduling using the cortex-a8 schedule model. The idea is that in-order cpu's require the most help in instruction scheduling, whereas out-of-order cpus can for the most part out-of-order schedule around different codegen. Our benchmarking suggests that hypothesis holds. When running on an in-order core this improved performance by 3.8% geomean on a set of DSP workloads, 2% geomean on some other embedded benchmark and between 1% and 1.8% on a set of singlecore and multicore workloads, all running on a Cortex-A55 cluster. On an out-of-order cpu the results are a lot more noisy but show flat performance or an improvement. On the set of DSP and embedded benchmarks, run on a Cortex-A78 there was a very noisy 1% speed improvement. Using the most detailed results I could find, SPEC2006 runs on a Neoverse N1 show a small increase in instruction count (+0.127%), but a decrease in cycle counts (-0.155%, on average). The instruction count is very low noise, the cycle count is more noisy with a 0.15% decrease not being significant. SPEC2k17 shows a small decrease (-0.2%) in instruction count leading to a -0.296% decrease in cycle count. These results are within noise margins but tend to show a small improvement in general. When specifying an Apple target, clang will set "-target-cpu apple-a7" on the command line, so should not be affected by this change when running from clang. This also doesn't enable more runtime unrolling like -mcpu=cortex-a55 does, only changing the schedule used. A lot of existing tests have updated. This is a summary of the important differences: - Most changes are the same instructions in a different order. - Sometimes this leads to very minor inefficiencies, such as requiring an extra mov to move variables into r0/v0 for the return value of a test function. - misched-fusion.ll was no longer fusing the pairs of instructions it should, as per D110561. I've changed the schedule used in the test for now. - neon-mla-mls.ll now uses "mul; sub" as opposed to "neg; mla" due to the different latencies. This seems fine to me. - Some SVE tests do not always remove movprfx where they did before due to different register allocation giving different destructive forms. - The tests argument-blocks-array-of-struct.ll and arm64-windows-calls.ll produce two LDR where they previously produced an LDP due to store-pair-suppress kicking in. - arm64-ldp.ll and arm64-neon-copy.ll are missing pre/postinc on LPD. - Some tests such as arm64-neon-mul-div.ll and ragreedy-local-interval-cost.ll have more, less or just different spilling. - In aarch64_generated_funcs.ll.generated.expected one part of the function is no longer outlined. Interestingly if I switch this to use any other scheduled even less is outlined. Some of these are expected to happen, such as differences in outlining or register spilling. There will be places where these result in worse codegen, places where they are better, with the SPEC instruction counts suggesting it is not a decrease overall, on average. Differential Revision: https://reviews.llvm.org/D110830
152 lines
4.0 KiB
LLVM
152 lines
4.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64 < %s | FileCheck %s
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; Check that we optimize out AND instructions and ADD/SUB instructions
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; modulo the shift size to take advantage of the implicit mod done on
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; the shift amount value by the variable shift/rotate instructions.
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define i32 @test1(i32 %x, i64 %y) {
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; CHECK-LABEL: test1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: lsr w0, w0, w1
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; CHECK-NEXT: ret
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%sh_prom = trunc i64 %y to i32
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%shr = lshr i32 %x, %sh_prom
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ret i32 %shr
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}
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define i64 @test2(i32 %x, i64 %y) {
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; CHECK-LABEL: test2:
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; CHECK: // %bb.0:
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; CHECK-NEXT: neg w8, w0
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; CHECK-NEXT: asr x0, x1, x8
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; CHECK-NEXT: ret
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%sub9 = sub nsw i32 64, %x
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%sh_prom12.i = zext i32 %sub9 to i64
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%shr.i = ashr i64 %y, %sh_prom12.i
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ret i64 %shr.i
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}
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define i64 @test3(i64 %x, i64 %y) {
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; CHECK-LABEL: test3:
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; CHECK: // %bb.0:
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; CHECK-NEXT: lsl x0, x1, x0
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; CHECK-NEXT: ret
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%add = add nsw i64 64, %x
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%shl = shl i64 %y, %add
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ret i64 %shl
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}
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define i64 @test4(i64 %y, i32 %s) {
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; CHECK-LABEL: test4:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: // kill: def $w1 killed $w1 def $x1
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; CHECK-NEXT: asr x0, x0, x1
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; CHECK-NEXT: ret
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entry:
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%sh_prom = zext i32 %s to i64
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%shr = ashr i64 %y, %sh_prom
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ret i64 %shr
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}
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define i64 @test5(i64 %y, i32 %s) {
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; CHECK-LABEL: test5:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: // kill: def $w1 killed $w1 def $x1
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; CHECK-NEXT: asr x0, x0, x1
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; CHECK-NEXT: ret
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entry:
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%sh_prom = sext i32 %s to i64
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%shr = ashr i64 %y, %sh_prom
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ret i64 %shr
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}
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define i64 @test6(i64 %y, i32 %s) {
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; CHECK-LABEL: test6:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: // kill: def $w1 killed $w1 def $x1
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; CHECK-NEXT: lsl x0, x0, x1
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; CHECK-NEXT: ret
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entry:
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%sh_prom = sext i32 %s to i64
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%shr = shl i64 %y, %sh_prom
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ret i64 %shr
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}
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; PR42644 - https://bugs.llvm.org/show_bug.cgi?id=42644
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define i64 @ashr_add_shl_i32(i64 %r) {
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; CHECK-LABEL: ashr_add_shl_i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: add w8, w0, #1
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; CHECK-NEXT: sxtw x0, w8
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; CHECK-NEXT: ret
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%conv = shl i64 %r, 32
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%sext = add i64 %conv, 4294967296
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%conv1 = ashr i64 %sext, 32
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ret i64 %conv1
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}
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define i64 @ashr_add_shl_i8(i64 %r) {
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; CHECK-LABEL: ashr_add_shl_i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: add w8, w0, #1
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; CHECK-NEXT: sxtb x0, w8
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; CHECK-NEXT: ret
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%conv = shl i64 %r, 56
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%sext = add i64 %conv, 72057594037927936
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%conv1 = ashr i64 %sext, 56
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ret i64 %conv1
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}
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define <4 x i32> @ashr_add_shl_v4i8(<4 x i32> %r) {
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; CHECK-LABEL: ashr_add_shl_v4i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: movi v1.4s, #1, lsl #24
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; CHECK-NEXT: shl v0.4s, v0.4s, #24
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; CHECK-NEXT: add v0.4s, v0.4s, v1.4s
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; CHECK-NEXT: sshr v0.4s, v0.4s, #24
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; CHECK-NEXT: ret
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%conv = shl <4 x i32> %r, <i32 24, i32 24, i32 24, i32 24>
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%sext = add <4 x i32> %conv, <i32 16777216, i32 16777216, i32 16777216, i32 16777216>
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%conv1 = ashr <4 x i32> %sext, <i32 24, i32 24, i32 24, i32 24>
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ret <4 x i32> %conv1
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}
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define i64 @ashr_add_shl_i36(i64 %r) {
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; CHECK-LABEL: ashr_add_shl_i36:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sbfx x0, x0, #0, #28
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; CHECK-NEXT: ret
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%conv = shl i64 %r, 36
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%sext = add i64 %conv, 4294967296
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%conv1 = ashr i64 %sext, 36
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ret i64 %conv1
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}
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define i64 @ashr_add_shl_mismatch_shifts1(i64 %r) {
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; CHECK-LABEL: ashr_add_shl_mismatch_shifts1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov x8, #4294967296
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; CHECK-NEXT: add x8, x8, x0, lsl #8
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; CHECK-NEXT: asr x0, x8, #32
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; CHECK-NEXT: ret
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%conv = shl i64 %r, 8
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%sext = add i64 %conv, 4294967296
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%conv1 = ashr i64 %sext, 32
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ret i64 %conv1
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}
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define i64 @ashr_add_shl_mismatch_shifts2(i64 %r) {
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; CHECK-LABEL: ashr_add_shl_mismatch_shifts2:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov x8, #4294967296
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; CHECK-NEXT: add x8, x8, x0, lsr #8
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; CHECK-NEXT: lsr x0, x8, #8
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; CHECK-NEXT: ret
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%conv = lshr i64 %r, 8
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%sext = add i64 %conv, 4294967296
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%conv1 = ashr i64 %sext, 8
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ret i64 %conv1
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}
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