9e9907f1cf
Similar to 806761a7629df268c8aed49657aeccffa6bca449. For IR files without a target triple, -mtriple= specifies the full target triple while -march= merely sets the architecture part of the default target triple, leaving a target triple which may not make sense, e.g. amdgpu-apple-darwin. Therefore, -march= is error-prone and not recommended for tests without a target triple. The issue has been benign as we recognize $unknown-apple-darwin as ELF instead of rejecting it outrightly. This patch changes AMDGPU tests to not rely on the default OS/environment components. Tests that need fixes are not changed: ``` LLVM :: CodeGen/AMDGPU/fabs.f64.ll LLVM :: CodeGen/AMDGPU/fabs.ll LLVM :: CodeGen/AMDGPU/floor.ll LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll LLVM :: CodeGen/AMDGPU/fneg-fabs.ll LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll LLVM :: CodeGen/AMDGPU/schedule-if-2.ll ```
426 lines
17 KiB
YAML
426 lines
17 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck -check-prefix=WAVE64 %s
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# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck -check-prefix=WAVE64 %s
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# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck -check-prefix=WAVE32 %s
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# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck -check-prefix=WAVE32 %s
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---
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name: test_dyn_stackalloc_sgpr_align1
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legalized: true
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frameInfo:
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maxAlignment: 2
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stack:
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- { id: 0, type: variable-sized, alignment: 1 }
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body: |
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bb.0:
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liveins: $sgpr0
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; WAVE64-LABEL: name: test_dyn_stackalloc_sgpr_align1
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; WAVE64: liveins: $sgpr0
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; WAVE64-NEXT: {{ $}}
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; WAVE64-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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; WAVE64-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 6
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; WAVE64-NEXT: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[COPY]], [[C]](s32)
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; WAVE64-NEXT: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
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; WAVE64-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[SHL]](s32)
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; WAVE64-NEXT: S_ENDPGM 0, implicit [[PTR_ADD]](p5)
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; WAVE32-LABEL: name: test_dyn_stackalloc_sgpr_align1
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; WAVE32: liveins: $sgpr0
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; WAVE32-NEXT: {{ $}}
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; WAVE32-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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; WAVE32-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 5
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; WAVE32-NEXT: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[COPY]], [[C]](s32)
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; WAVE32-NEXT: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
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; WAVE32-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[SHL]](s32)
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; WAVE32-NEXT: S_ENDPGM 0, implicit [[PTR_ADD]](p5)
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%0:_(s32) = COPY $sgpr0
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%1:_(p5) = G_DYN_STACKALLOC %0, 1
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S_ENDPGM 0, implicit %1
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...
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---
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name: test_dyn_stackalloc_sgpr_align2
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legalized: true
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frameInfo:
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maxAlignment: 2
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stack:
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- { id: 0, type: variable-sized, alignment: 2 }
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body: |
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bb.0:
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liveins: $sgpr0
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; WAVE64-LABEL: name: test_dyn_stackalloc_sgpr_align2
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; WAVE64: liveins: $sgpr0
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; WAVE64-NEXT: {{ $}}
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; WAVE64-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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; WAVE64-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 6
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; WAVE64-NEXT: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[COPY]], [[C]](s32)
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; WAVE64-NEXT: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
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; WAVE64-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[SHL]](s32)
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; WAVE64-NEXT: S_ENDPGM 0, implicit [[PTR_ADD]](p5)
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; WAVE32-LABEL: name: test_dyn_stackalloc_sgpr_align2
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; WAVE32: liveins: $sgpr0
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; WAVE32-NEXT: {{ $}}
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; WAVE32-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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; WAVE32-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 5
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; WAVE32-NEXT: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[COPY]], [[C]](s32)
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; WAVE32-NEXT: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
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; WAVE32-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[SHL]](s32)
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; WAVE32-NEXT: S_ENDPGM 0, implicit [[PTR_ADD]](p5)
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%0:_(s32) = COPY $sgpr0
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%1:_(p5) = G_DYN_STACKALLOC %0, 2
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S_ENDPGM 0, implicit %1
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...
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---
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name: test_dyn_stackalloc_sgpr_align4
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legalized: true
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frameInfo:
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maxAlignment: 4
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stack:
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- { id: 0, type: variable-sized, alignment: 4 }
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body: |
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bb.0:
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liveins: $sgpr0
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; WAVE64-LABEL: name: test_dyn_stackalloc_sgpr_align4
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; WAVE64: liveins: $sgpr0
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; WAVE64-NEXT: {{ $}}
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; WAVE64-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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; WAVE64-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 6
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; WAVE64-NEXT: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[COPY]], [[C]](s32)
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; WAVE64-NEXT: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
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; WAVE64-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[SHL]](s32)
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; WAVE64-NEXT: S_ENDPGM 0, implicit [[PTR_ADD]](p5)
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; WAVE32-LABEL: name: test_dyn_stackalloc_sgpr_align4
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; WAVE32: liveins: $sgpr0
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; WAVE32-NEXT: {{ $}}
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; WAVE32-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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; WAVE32-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 5
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; WAVE32-NEXT: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[COPY]], [[C]](s32)
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; WAVE32-NEXT: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
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; WAVE32-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[SHL]](s32)
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; WAVE32-NEXT: S_ENDPGM 0, implicit [[PTR_ADD]](p5)
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%0:_(s32) = COPY $sgpr0
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%1:_(p5) = G_DYN_STACKALLOC %0, 4
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S_ENDPGM 0, implicit %1
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...
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---
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name: test_dyn_stackalloc_sgpr_align8
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legalized: true
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frameInfo:
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maxAlignment: 8
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stack:
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- { id: 0, type: variable-sized, alignment: 8 }
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body: |
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bb.0:
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liveins: $sgpr0
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; WAVE64-LABEL: name: test_dyn_stackalloc_sgpr_align8
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; WAVE64: liveins: $sgpr0
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; WAVE64-NEXT: {{ $}}
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; WAVE64-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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; WAVE64-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 6
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; WAVE64-NEXT: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[COPY]], [[C]](s32)
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; WAVE64-NEXT: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
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; WAVE64-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[SHL]](s32)
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; WAVE64-NEXT: S_ENDPGM 0, implicit [[PTR_ADD]](p5)
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; WAVE32-LABEL: name: test_dyn_stackalloc_sgpr_align8
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; WAVE32: liveins: $sgpr0
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; WAVE32-NEXT: {{ $}}
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; WAVE32-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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; WAVE32-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 5
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; WAVE32-NEXT: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[COPY]], [[C]](s32)
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; WAVE32-NEXT: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
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; WAVE32-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[SHL]](s32)
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; WAVE32-NEXT: S_ENDPGM 0, implicit [[PTR_ADD]](p5)
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%0:_(s32) = COPY $sgpr0
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%1:_(p5) = G_DYN_STACKALLOC %0, 8
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S_ENDPGM 0, implicit %1
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...
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---
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name: test_dyn_stackalloc_sgpr_align16
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legalized: true
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frameInfo:
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maxAlignment: 16
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stack:
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- { id: 0, type: variable-sized, alignment: 16 }
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body: |
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bb.0:
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liveins: $sgpr0
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; WAVE64-LABEL: name: test_dyn_stackalloc_sgpr_align16
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; WAVE64: liveins: $sgpr0
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; WAVE64-NEXT: {{ $}}
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; WAVE64-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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; WAVE64-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 6
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; WAVE64-NEXT: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[COPY]], [[C]](s32)
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; WAVE64-NEXT: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
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; WAVE64-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[SHL]](s32)
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; WAVE64-NEXT: S_ENDPGM 0, implicit [[PTR_ADD]](p5)
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; WAVE32-LABEL: name: test_dyn_stackalloc_sgpr_align16
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; WAVE32: liveins: $sgpr0
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; WAVE32-NEXT: {{ $}}
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; WAVE32-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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; WAVE32-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 5
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; WAVE32-NEXT: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[COPY]], [[C]](s32)
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; WAVE32-NEXT: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
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; WAVE32-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[SHL]](s32)
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; WAVE32-NEXT: S_ENDPGM 0, implicit [[PTR_ADD]](p5)
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%0:_(s32) = COPY $sgpr0
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%1:_(p5) = G_DYN_STACKALLOC %0, 16
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S_ENDPGM 0, implicit %1
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...
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---
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name: test_dyn_stackalloc_sgpr_align32
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legalized: true
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frameInfo:
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maxAlignment: 32
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stack:
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- { id: 0, type: variable-sized, alignment: 32 }
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body: |
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bb.0:
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liveins: $sgpr0
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; WAVE64-LABEL: name: test_dyn_stackalloc_sgpr_align32
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; WAVE64: liveins: $sgpr0
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; WAVE64-NEXT: {{ $}}
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; WAVE64-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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; WAVE64-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 6
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; WAVE64-NEXT: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[COPY]], [[C]](s32)
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; WAVE64-NEXT: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
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; WAVE64-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[SHL]](s32)
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; WAVE64-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 -2048
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; WAVE64-NEXT: [[PTRMASK:%[0-9]+]]:sgpr(p5) = G_PTRMASK [[PTR_ADD]], [[C1]](s32)
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; WAVE64-NEXT: S_ENDPGM 0, implicit [[PTRMASK]](p5)
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; WAVE32-LABEL: name: test_dyn_stackalloc_sgpr_align32
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; WAVE32: liveins: $sgpr0
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; WAVE32-NEXT: {{ $}}
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; WAVE32-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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; WAVE32-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 5
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; WAVE32-NEXT: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[COPY]], [[C]](s32)
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; WAVE32-NEXT: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
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; WAVE32-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[SHL]](s32)
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; WAVE32-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 -1024
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; WAVE32-NEXT: [[PTRMASK:%[0-9]+]]:sgpr(p5) = G_PTRMASK [[PTR_ADD]], [[C1]](s32)
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; WAVE32-NEXT: S_ENDPGM 0, implicit [[PTRMASK]](p5)
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%0:_(s32) = COPY $sgpr0
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%1:_(p5) = G_DYN_STACKALLOC %0, 32
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S_ENDPGM 0, implicit %1
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...
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---
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name: test_dyn_stackalloc_sgpr_align64
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legalized: true
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frameInfo:
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maxAlignment: 64
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stack:
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- { id: 0, type: variable-sized, alignment: 64 }
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body: |
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bb.0:
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liveins: $sgpr0
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; WAVE64-LABEL: name: test_dyn_stackalloc_sgpr_align64
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; WAVE64: liveins: $sgpr0
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; WAVE64-NEXT: {{ $}}
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; WAVE64-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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; WAVE64-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 6
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; WAVE64-NEXT: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[COPY]], [[C]](s32)
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; WAVE64-NEXT: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
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; WAVE64-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[SHL]](s32)
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; WAVE64-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 -4096
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; WAVE64-NEXT: [[PTRMASK:%[0-9]+]]:sgpr(p5) = G_PTRMASK [[PTR_ADD]], [[C1]](s32)
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; WAVE64-NEXT: S_ENDPGM 0, implicit [[PTRMASK]](p5)
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; WAVE32-LABEL: name: test_dyn_stackalloc_sgpr_align64
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; WAVE32: liveins: $sgpr0
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; WAVE32-NEXT: {{ $}}
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; WAVE32-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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; WAVE32-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 5
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; WAVE32-NEXT: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[COPY]], [[C]](s32)
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; WAVE32-NEXT: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
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; WAVE32-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[SHL]](s32)
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; WAVE32-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 -2048
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; WAVE32-NEXT: [[PTRMASK:%[0-9]+]]:sgpr(p5) = G_PTRMASK [[PTR_ADD]], [[C1]](s32)
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; WAVE32-NEXT: S_ENDPGM 0, implicit [[PTRMASK]](p5)
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%0:_(s32) = COPY $sgpr0
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%1:_(p5) = G_DYN_STACKALLOC %0, 64
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S_ENDPGM 0, implicit %1
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...
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---
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name: test_dyn_stackalloc_sgpr_align128
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legalized: true
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frameInfo:
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maxAlignment: 64
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stack:
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- { id: 0, type: variable-sized, alignment: 128 }
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body: |
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bb.0:
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liveins: $sgpr0
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; WAVE64-LABEL: name: test_dyn_stackalloc_sgpr_align128
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; WAVE64: liveins: $sgpr0
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; WAVE64-NEXT: {{ $}}
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; WAVE64-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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; WAVE64-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 6
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; WAVE64-NEXT: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[COPY]], [[C]](s32)
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; WAVE64-NEXT: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
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; WAVE64-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[SHL]](s32)
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; WAVE64-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 -8192
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; WAVE64-NEXT: [[PTRMASK:%[0-9]+]]:sgpr(p5) = G_PTRMASK [[PTR_ADD]], [[C1]](s32)
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; WAVE64-NEXT: S_ENDPGM 0, implicit [[PTRMASK]](p5)
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; WAVE32-LABEL: name: test_dyn_stackalloc_sgpr_align128
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; WAVE32: liveins: $sgpr0
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; WAVE32-NEXT: {{ $}}
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; WAVE32-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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; WAVE32-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 5
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; WAVE32-NEXT: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[COPY]], [[C]](s32)
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; WAVE32-NEXT: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
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; WAVE32-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[SHL]](s32)
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; WAVE32-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 -4096
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; WAVE32-NEXT: [[PTRMASK:%[0-9]+]]:sgpr(p5) = G_PTRMASK [[PTR_ADD]], [[C1]](s32)
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; WAVE32-NEXT: S_ENDPGM 0, implicit [[PTRMASK]](p5)
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%0:_(s32) = COPY $sgpr0
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%1:_(p5) = G_DYN_STACKALLOC %0, 128
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S_ENDPGM 0, implicit %1
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...
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---
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name: test_dyn_stackalloc_sgpr_constant_align4
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legalized: true
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frameInfo:
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maxAlignment: 4
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stack:
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- { id: 0, type: variable-sized, alignment: 4 }
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body: |
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bb.0:
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; WAVE64-LABEL: name: test_dyn_stackalloc_sgpr_constant_align4
|
|
; WAVE64: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 32
|
|
; WAVE64-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 6
|
|
; WAVE64-NEXT: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[C]], [[C1]](s32)
|
|
; WAVE64-NEXT: [[COPY:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
|
|
; WAVE64-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY]], [[SHL]](s32)
|
|
; WAVE64-NEXT: S_ENDPGM 0, implicit [[PTR_ADD]](p5)
|
|
; WAVE32-LABEL: name: test_dyn_stackalloc_sgpr_constant_align4
|
|
; WAVE32: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 32
|
|
; WAVE32-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 5
|
|
; WAVE32-NEXT: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[C]], [[C1]](s32)
|
|
; WAVE32-NEXT: [[COPY:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
|
|
; WAVE32-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY]], [[SHL]](s32)
|
|
; WAVE32-NEXT: S_ENDPGM 0, implicit [[PTR_ADD]](p5)
|
|
%0:_(s32) = G_CONSTANT i32 32
|
|
%1:_(p5) = G_DYN_STACKALLOC %0, 4
|
|
S_ENDPGM 0, implicit %1
|
|
...
|
|
|
|
---
|
|
name: test_dyn_stackalloc_sgpr_constant_align8
|
|
legalized: true
|
|
frameInfo:
|
|
maxAlignment: 8
|
|
stack:
|
|
- { id: 0, type: variable-sized, alignment: 8 }
|
|
body: |
|
|
bb.0:
|
|
liveins: $sgpr0
|
|
|
|
; WAVE64-LABEL: name: test_dyn_stackalloc_sgpr_constant_align8
|
|
; WAVE64: liveins: $sgpr0
|
|
; WAVE64-NEXT: {{ $}}
|
|
; WAVE64-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 32
|
|
; WAVE64-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 6
|
|
; WAVE64-NEXT: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[C]], [[C1]](s32)
|
|
; WAVE64-NEXT: [[COPY:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
|
|
; WAVE64-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY]], [[SHL]](s32)
|
|
; WAVE64-NEXT: S_ENDPGM 0, implicit [[PTR_ADD]](p5)
|
|
; WAVE32-LABEL: name: test_dyn_stackalloc_sgpr_constant_align8
|
|
; WAVE32: liveins: $sgpr0
|
|
; WAVE32-NEXT: {{ $}}
|
|
; WAVE32-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 32
|
|
; WAVE32-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 5
|
|
; WAVE32-NEXT: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[C]], [[C1]](s32)
|
|
; WAVE32-NEXT: [[COPY:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
|
|
; WAVE32-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY]], [[SHL]](s32)
|
|
; WAVE32-NEXT: S_ENDPGM 0, implicit [[PTR_ADD]](p5)
|
|
%0:_(s32) = G_CONSTANT i32 32
|
|
%1:_(p5) = G_DYN_STACKALLOC %0, 8
|
|
S_ENDPGM 0, implicit %1
|
|
...
|
|
|
|
---
|
|
name: test_dyn_stackalloc_sgpr_constant_align16
|
|
legalized: true
|
|
frameInfo:
|
|
maxAlignment: 16
|
|
stack:
|
|
- { id: 0, type: variable-sized, alignment: 16 }
|
|
body: |
|
|
bb.0:
|
|
liveins: $sgpr0
|
|
|
|
; WAVE64-LABEL: name: test_dyn_stackalloc_sgpr_constant_align16
|
|
; WAVE64: liveins: $sgpr0
|
|
; WAVE64-NEXT: {{ $}}
|
|
; WAVE64-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 32
|
|
; WAVE64-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 6
|
|
; WAVE64-NEXT: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[C]], [[C1]](s32)
|
|
; WAVE64-NEXT: [[COPY:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
|
|
; WAVE64-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY]], [[SHL]](s32)
|
|
; WAVE64-NEXT: S_ENDPGM 0, implicit [[PTR_ADD]](p5)
|
|
; WAVE32-LABEL: name: test_dyn_stackalloc_sgpr_constant_align16
|
|
; WAVE32: liveins: $sgpr0
|
|
; WAVE32-NEXT: {{ $}}
|
|
; WAVE32-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 32
|
|
; WAVE32-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 5
|
|
; WAVE32-NEXT: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[C]], [[C1]](s32)
|
|
; WAVE32-NEXT: [[COPY:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
|
|
; WAVE32-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY]], [[SHL]](s32)
|
|
; WAVE32-NEXT: S_ENDPGM 0, implicit [[PTR_ADD]](p5)
|
|
%0:_(s32) = G_CONSTANT i32 32
|
|
%1:_(p5) = G_DYN_STACKALLOC %0, 16
|
|
S_ENDPGM 0, implicit %1
|
|
...
|
|
|
|
---
|
|
name: test_dyn_stackalloc_sgpr_constant_align32
|
|
legalized: true
|
|
frameInfo:
|
|
maxAlignment: 32
|
|
stack:
|
|
- { id: 0, type: variable-sized, alignment: 32 }
|
|
body: |
|
|
bb.0:
|
|
liveins: $sgpr0
|
|
|
|
; WAVE64-LABEL: name: test_dyn_stackalloc_sgpr_constant_align32
|
|
; WAVE64: liveins: $sgpr0
|
|
; WAVE64-NEXT: {{ $}}
|
|
; WAVE64-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 32
|
|
; WAVE64-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 6
|
|
; WAVE64-NEXT: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[C]], [[C1]](s32)
|
|
; WAVE64-NEXT: [[COPY:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
|
|
; WAVE64-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY]], [[SHL]](s32)
|
|
; WAVE64-NEXT: [[C2:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 -2048
|
|
; WAVE64-NEXT: [[PTRMASK:%[0-9]+]]:sgpr(p5) = G_PTRMASK [[PTR_ADD]], [[C2]](s32)
|
|
; WAVE64-NEXT: S_ENDPGM 0, implicit [[PTRMASK]](p5)
|
|
; WAVE32-LABEL: name: test_dyn_stackalloc_sgpr_constant_align32
|
|
; WAVE32: liveins: $sgpr0
|
|
; WAVE32-NEXT: {{ $}}
|
|
; WAVE32-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 32
|
|
; WAVE32-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 5
|
|
; WAVE32-NEXT: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[C]], [[C1]](s32)
|
|
; WAVE32-NEXT: [[COPY:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
|
|
; WAVE32-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY]], [[SHL]](s32)
|
|
; WAVE32-NEXT: [[C2:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 -1024
|
|
; WAVE32-NEXT: [[PTRMASK:%[0-9]+]]:sgpr(p5) = G_PTRMASK [[PTR_ADD]], [[C2]](s32)
|
|
; WAVE32-NEXT: S_ENDPGM 0, implicit [[PTRMASK]](p5)
|
|
%0:_(s32) = G_CONSTANT i32 32
|
|
%1:_(p5) = G_DYN_STACKALLOC %0, 32
|
|
S_ENDPGM 0, implicit %1
|
|
...
|