9e9907f1cf
Similar to 806761a7629df268c8aed49657aeccffa6bca449. For IR files without a target triple, -mtriple= specifies the full target triple while -march= merely sets the architecture part of the default target triple, leaving a target triple which may not make sense, e.g. amdgpu-apple-darwin. Therefore, -march= is error-prone and not recommended for tests without a target triple. The issue has been benign as we recognize $unknown-apple-darwin as ELF instead of rejecting it outrightly. This patch changes AMDGPU tests to not rely on the default OS/environment components. Tests that need fixes are not changed: ``` LLVM :: CodeGen/AMDGPU/fabs.f64.ll LLVM :: CodeGen/AMDGPU/fabs.ll LLVM :: CodeGen/AMDGPU/floor.ll LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll LLVM :: CodeGen/AMDGPU/fneg-fabs.ll LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll LLVM :: CodeGen/AMDGPU/schedule-if-2.ll ```
85 lines
3.2 KiB
LLVM
85 lines
3.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=r600 -mcpu=cayman < %s | FileCheck %s
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define amdgpu_kernel void @addrspacecast_flat_to_global(ptr addrspace(1) %out, ptr %src.ptr) {
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; CHECK-LABEL: addrspacecast_flat_to_global:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]
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; CHECK-NEXT: MEM_RAT_CACHELESS STORE_DWORD T1.X, T0.X
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; CHECK-NEXT: CF_END
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; CHECK-NEXT: PAD
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; CHECK-NEXT: ALU clause starting at 4:
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; CHECK-NEXT: LSHR * T0.X, KC0[2].Y, literal.x,
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; CHECK-NEXT: 2(2.802597e-45), 0(0.000000e+00)
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; CHECK-NEXT: MOV * T1.X, KC0[2].Z,
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%cast = addrspacecast ptr %src.ptr to ptr addrspace(1)
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store ptr addrspace(1) %cast, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_kernel void @addrspacecast_global_to_flat(ptr addrspace(1) %out, ptr addrspace(1) %src.ptr) {
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; CHECK-LABEL: addrspacecast_global_to_flat:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]
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; CHECK-NEXT: MEM_RAT_CACHELESS STORE_DWORD T1.X, T0.X
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; CHECK-NEXT: CF_END
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; CHECK-NEXT: PAD
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; CHECK-NEXT: ALU clause starting at 4:
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; CHECK-NEXT: LSHR * T0.X, KC0[2].Y, literal.x,
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; CHECK-NEXT: 2(2.802597e-45), 0(0.000000e+00)
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; CHECK-NEXT: MOV * T1.X, KC0[2].Z,
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%cast = addrspacecast ptr addrspace(1) %src.ptr to ptr
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store ptr %cast, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_kernel void @addrspacecast_flat_null_to_local(ptr addrspace(1) %out) {
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; CHECK-LABEL: addrspacecast_flat_null_to_local:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: ALU 3, @4, KC0[CB0:0-32], KC1[]
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; CHECK-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0.X, T1.X
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; CHECK-NEXT: CF_END
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; CHECK-NEXT: PAD
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; CHECK-NEXT: ALU clause starting at 4:
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; CHECK-NEXT: MOV * T0.X, literal.x,
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; CHECK-NEXT: -1(nan), 0(0.000000e+00)
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; CHECK-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
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; CHECK-NEXT: 2(2.802597e-45), 0(0.000000e+00)
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store ptr addrspace(3) addrspacecast (ptr null to ptr addrspace(3)), ptr addrspace(1) %out
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ret void
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}
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define amdgpu_kernel void @addrspacecast_flat_null_to_global(ptr addrspace(1) %out) {
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; CHECK-LABEL: addrspacecast_flat_null_to_global:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: ALU 3, @4, KC0[CB0:0-32], KC1[]
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; CHECK-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0.X, T1.X
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; CHECK-NEXT: CF_END
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; CHECK-NEXT: PAD
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; CHECK-NEXT: ALU clause starting at 4:
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; CHECK-NEXT: MOV * T0.X, literal.x,
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; CHECK-NEXT: 0(0.000000e+00), 0(0.000000e+00)
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; CHECK-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
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; CHECK-NEXT: 2(2.802597e-45), 0(0.000000e+00)
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store ptr addrspace(1) addrspacecast (ptr null to ptr addrspace(1)), ptr addrspace(1) %out
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ret void
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}
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define amdgpu_kernel void @addrspacecast_flat_undef_to_local(ptr addrspace(1) %out) {
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; CHECK-LABEL: addrspacecast_flat_undef_to_local:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: CF_END
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; CHECK-NEXT: PAD
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store ptr addrspace(3) addrspacecast (ptr undef to ptr addrspace(3)), ptr addrspace(1) %out
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ret void
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}
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define amdgpu_kernel void @addrspacecast_flat_poison_to_local(ptr addrspace(1) %out) {
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; CHECK-LABEL: addrspacecast_flat_poison_to_local:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: CF_END
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; CHECK-NEXT: PAD
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store ptr addrspace(3) addrspacecast (ptr poison to ptr addrspace(3)), ptr addrspace(1) %out
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ret void
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}
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