9e9907f1cf
Similar to 806761a7629df268c8aed49657aeccffa6bca449. For IR files without a target triple, -mtriple= specifies the full target triple while -march= merely sets the architecture part of the default target triple, leaving a target triple which may not make sense, e.g. amdgpu-apple-darwin. Therefore, -march= is error-prone and not recommended for tests without a target triple. The issue has been benign as we recognize $unknown-apple-darwin as ELF instead of rejecting it outrightly. This patch changes AMDGPU tests to not rely on the default OS/environment components. Tests that need fixes are not changed: ``` LLVM :: CodeGen/AMDGPU/fabs.f64.ll LLVM :: CodeGen/AMDGPU/fabs.ll LLVM :: CodeGen/AMDGPU/floor.ll LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll LLVM :: CodeGen/AMDGPU/fneg-fabs.ll LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll LLVM :: CodeGen/AMDGPU/schedule-if-2.ll ```
104 lines
3.0 KiB
LLVM
104 lines
3.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck %s --check-prefix=GFX9
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck %s --check-prefix=GFX10
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck %s --check-prefix=GFX11
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define amdgpu_kernel void @test0() {
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; GFX9-LABEL: test0:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_endpgm
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;
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; GFX10-LABEL: test0:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: s_endpgm
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;
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; GFX11-LABEL: test0:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_endpgm
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tail call void @llvm.amdgcn.endpgm()
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unreachable
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}
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define void @test1() {
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; GFX9-LABEL: test1:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX9-NEXT: s_endpgm
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;
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; GFX10-LABEL: test1:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX10-NEXT: s_endpgm
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;
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; GFX11-LABEL: test1:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX11-NEXT: s_endpgm
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tail call void @llvm.amdgcn.endpgm()
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unreachable
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}
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define amdgpu_kernel void @test2(ptr %p, i32 %x) {
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; GFX9-LABEL: test2:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_load_dword s2, s[0:1], 0x2c
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; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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; GFX9-NEXT: s_cmp_lt_i32 s2, 1
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; GFX9-NEXT: s_cbranch_scc0 .LBB2_2
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; GFX9-NEXT: ; %bb.1: ; %else
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; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
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; GFX9-NEXT: v_mov_b32_e32 v2, s2
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; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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; GFX9-NEXT: v_mov_b32_e32 v0, s0
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; GFX9-NEXT: v_mov_b32_e32 v1, s1
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; GFX9-NEXT: flat_store_dword v[0:1], v2
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; GFX9-NEXT: s_endpgm
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; GFX9-NEXT: .LBB2_2: ; %then
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; GFX9-NEXT: s_endpgm
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;
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; GFX10-LABEL: test2:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: s_load_dword s2, s[0:1], 0x2c
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; GFX10-NEXT: s_waitcnt lgkmcnt(0)
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; GFX10-NEXT: s_cmp_lt_i32 s2, 1
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; GFX10-NEXT: s_cbranch_scc0 .LBB2_2
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; GFX10-NEXT: ; %bb.1: ; %else
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; GFX10-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
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; GFX10-NEXT: v_mov_b32_e32 v2, s2
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; GFX10-NEXT: s_waitcnt lgkmcnt(0)
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; GFX10-NEXT: v_mov_b32_e32 v0, s0
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; GFX10-NEXT: v_mov_b32_e32 v1, s1
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; GFX10-NEXT: flat_store_dword v[0:1], v2
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; GFX10-NEXT: s_endpgm
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; GFX10-NEXT: .LBB2_2: ; %then
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; GFX10-NEXT: s_endpgm
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;
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; GFX11-LABEL: test2:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
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; GFX11-NEXT: s_waitcnt lgkmcnt(0)
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; GFX11-NEXT: s_cmp_lt_i32 s2, 1
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; GFX11-NEXT: s_cbranch_scc0 .LBB2_2
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; GFX11-NEXT: ; %bb.1: ; %else
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; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
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; GFX11-NEXT: v_mov_b32_e32 v2, s2
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; GFX11-NEXT: s_waitcnt lgkmcnt(0)
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; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
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; GFX11-NEXT: flat_store_b32 v[0:1], v2
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; GFX11-NEXT: s_endpgm
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; GFX11-NEXT: .LBB2_2: ; %then
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; GFX11-NEXT: s_endpgm
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%cond = icmp sgt i32 %x, 0
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br i1 %cond, label %then, label %else
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then:
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tail call void @llvm.amdgcn.endpgm()
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unreachable
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else:
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store i32 %x, ptr %p
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ret void
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}
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declare void @llvm.amdgcn.endpgm()
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