9e9907f1cf
Similar to 806761a7629df268c8aed49657aeccffa6bca449. For IR files without a target triple, -mtriple= specifies the full target triple while -march= merely sets the architecture part of the default target triple, leaving a target triple which may not make sense, e.g. amdgpu-apple-darwin. Therefore, -march= is error-prone and not recommended for tests without a target triple. The issue has been benign as we recognize $unknown-apple-darwin as ELF instead of rejecting it outrightly. This patch changes AMDGPU tests to not rely on the default OS/environment components. Tests that need fixes are not changed: ``` LLVM :: CodeGen/AMDGPU/fabs.f64.ll LLVM :: CodeGen/AMDGPU/fabs.ll LLVM :: CodeGen/AMDGPU/floor.ll LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll LLVM :: CodeGen/AMDGPU/fneg-fabs.ll LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll LLVM :: CodeGen/AMDGPU/schedule-if-2.ll ```
34 lines
1.4 KiB
LLVM
34 lines
1.4 KiB
LLVM
; RUN: llc -mtriple=amdgcn -verify-machineinstrs < %s | FileCheck %s
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; Test for a bug where DAGCombiner::ReassociateOps() was creating adds
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; with offset in the first operand and base pointers in the second.
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; CHECK-LABEL: {{^}}store_same_base_ptr:
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; CHECK: buffer_store_dword v{{[0-9]+}}, [[VADDR:v\[[0-9]+:[0-9]+\]]], [[SADDR:s\[[0-9]+:[0-9]+\]]]
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; CHECK: buffer_store_dword v{{[0-9]+}}, [[VADDR]], [[SADDR]]
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; CHECK: buffer_store_dword v{{[0-9]+}}, [[VADDR]], [[SADDR]]
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; CHECK: buffer_store_dword v{{[0-9]+}}, [[VADDR]], [[SADDR]]
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define amdgpu_kernel void @store_same_base_ptr(ptr addrspace(1) %out) {
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entry:
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%id = call i32 @llvm.amdgcn.workitem.id.x() #0
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%offset = sext i32 %id to i64
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%offset0 = add i64 %offset, 1027
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%ptr0 = getelementptr i32, ptr addrspace(1) %out, i64 %offset0
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store volatile i32 3, ptr addrspace(1) %ptr0
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%offset1 = add i64 %offset, 1026
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%ptr1 = getelementptr i32, ptr addrspace(1) %out, i64 %offset1
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store volatile i32 2, ptr addrspace(1) %ptr1
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%offset2 = add i64 %offset, 1025
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%ptr2 = getelementptr i32, ptr addrspace(1) %out, i64 %offset2
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store volatile i32 1, ptr addrspace(1) %ptr2
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%offset3 = add i64 %offset, 1024
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%ptr3 = getelementptr i32, ptr addrspace(1) %out, i64 %offset3
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store volatile i32 0, ptr addrspace(1) %ptr3
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #0
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attributes #0 = { nounwind readnone }
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