9e9907f1cf
Similar to 806761a7629df268c8aed49657aeccffa6bca449. For IR files without a target triple, -mtriple= specifies the full target triple while -march= merely sets the architecture part of the default target triple, leaving a target triple which may not make sense, e.g. amdgpu-apple-darwin. Therefore, -march= is error-prone and not recommended for tests without a target triple. The issue has been benign as we recognize $unknown-apple-darwin as ELF instead of rejecting it outrightly. This patch changes AMDGPU tests to not rely on the default OS/environment components. Tests that need fixes are not changed: ``` LLVM :: CodeGen/AMDGPU/fabs.f64.ll LLVM :: CodeGen/AMDGPU/fabs.ll LLVM :: CodeGen/AMDGPU/floor.ll LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll LLVM :: CodeGen/AMDGPU/fneg-fabs.ll LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll LLVM :: CodeGen/AMDGPU/schedule-if-2.ll ```
74 lines
2.2 KiB
LLVM
74 lines
2.2 KiB
LLVM
; RUN: llc -mtriple=amdgcn -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GCN %s
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; GCN-LABEL: name: uniform_imin
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; GCN: S_MIN_I32
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define amdgpu_kernel void @uniform_imin(ptr addrspace(1) %out, i32 %a, i32 %b) #0 {
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%cmp = icmp sle i32 %a, %b
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%val = select i1 %cmp, i32 %a, i32 %b
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store i32 %val, ptr addrspace(1) %out, align 4
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ret void
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}
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; GCN-LABEL: name: divergent_imin
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; GCN: V_MIN_I32_e64
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define void @divergent_imin(ptr addrspace(1) %out, i32 %a, i32 %b) #0 {
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%cmp = icmp sle i32 %a, %b
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%val = select i1 %cmp, i32 %a, i32 %b
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store i32 %val, ptr addrspace(1) %out, align 4
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ret void
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}
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; GCN-LABEL: name: uniform_umin
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; GCN: S_MIN_U32
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define amdgpu_kernel void @uniform_umin(ptr addrspace(1) %out, i32 %a, i32 %b) #0 {
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%tmp = icmp ule i32 %a, %b
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%val = select i1 %tmp, i32 %a, i32 %b
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store i32 %val, ptr addrspace(1) %out, align 8
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ret void
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}
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; GCN-LABEL: name: divergent_umin
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; GCN: V_MIN_U32_e64
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define void @divergent_umin(ptr addrspace(1) %out, i32 %a, i32 %b) #0 {
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%tmp = icmp ule i32 %a, %b
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%val = select i1 %tmp, i32 %a, i32 %b
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store i32 %val, ptr addrspace(1) %out, align 8
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ret void
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}
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; GCN-LABEL: name: uniform_imax
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; GCN: S_MAX_I32
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define amdgpu_kernel void @uniform_imax(ptr addrspace(1) %out, i32 %a, i32 %b) nounwind {
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%cmp = icmp sge i32 %a, %b
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%val = select i1 %cmp, i32 %a, i32 %b
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store i32 %val, ptr addrspace(1) %out, align 4
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ret void
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}
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; GCN-LABEL: name: divergent_imax
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; GCN: V_MAX_I32_e64
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define void @divergent_imax(ptr addrspace(1) %out, i32 %a, i32 %b) nounwind {
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%cmp = icmp sge i32 %a, %b
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%val = select i1 %cmp, i32 %a, i32 %b
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store i32 %val, ptr addrspace(1) %out, align 4
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ret void
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}
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; GCN-LABEL: name: uniform_umax
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; GCN: S_MAX_U32
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define amdgpu_kernel void @uniform_umax(ptr addrspace(1) %out, i32 %a, i32 %b) nounwind {
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%cmp = icmp uge i32 %a, %b
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%val = select i1 %cmp, i32 %a, i32 %b
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store i32 %val, ptr addrspace(1) %out, align 4
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ret void
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}
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; GCN-LABEL: name: divergent_umax
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; GCN: V_MAX_U32_e64
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define void @divergent_umax(ptr addrspace(1) %out, i32 %a, i32 %b) nounwind {
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%cmp = icmp uge i32 %a, %b
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%val = select i1 %cmp, i32 %a, i32 %b
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store i32 %val, ptr addrspace(1) %out, align 4
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ret void
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}
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