9e9907f1cf
Similar to 806761a7629df268c8aed49657aeccffa6bca449. For IR files without a target triple, -mtriple= specifies the full target triple while -march= merely sets the architecture part of the default target triple, leaving a target triple which may not make sense, e.g. amdgpu-apple-darwin. Therefore, -march= is error-prone and not recommended for tests without a target triple. The issue has been benign as we recognize $unknown-apple-darwin as ELF instead of rejecting it outrightly. This patch changes AMDGPU tests to not rely on the default OS/environment components. Tests that need fixes are not changed: ``` LLVM :: CodeGen/AMDGPU/fabs.f64.ll LLVM :: CodeGen/AMDGPU/fabs.ll LLVM :: CodeGen/AMDGPU/floor.ll LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll LLVM :: CodeGen/AMDGPU/fneg-fabs.ll LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll LLVM :: CodeGen/AMDGPU/schedule-if-2.ll ```
40 lines
1.9 KiB
LLVM
40 lines
1.9 KiB
LLVM
; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=FUNC -check-prefix=SI %s
|
|
; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=FUNC -check-prefix=SI %s
|
|
|
|
; FUNC-LABEL: {{^}}fmul_f64:
|
|
; SI: v_mul_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}}
|
|
define amdgpu_kernel void @fmul_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1,
|
|
ptr addrspace(1) %in2) {
|
|
%r0 = load double, ptr addrspace(1) %in1
|
|
%r1 = load double, ptr addrspace(1) %in2
|
|
%r2 = fmul double %r0, %r1
|
|
store double %r2, ptr addrspace(1) %out
|
|
ret void
|
|
}
|
|
|
|
; FUNC-LABEL: {{^}}fmul_v2f64:
|
|
; SI: v_mul_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}}
|
|
; SI: v_mul_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}}
|
|
define amdgpu_kernel void @fmul_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %in1,
|
|
ptr addrspace(1) %in2) {
|
|
%r0 = load <2 x double>, ptr addrspace(1) %in1
|
|
%r1 = load <2 x double>, ptr addrspace(1) %in2
|
|
%r2 = fmul <2 x double> %r0, %r1
|
|
store <2 x double> %r2, ptr addrspace(1) %out
|
|
ret void
|
|
}
|
|
|
|
; FUNC-LABEL: {{^}}fmul_v4f64:
|
|
; SI: v_mul_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}}
|
|
; SI: v_mul_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}}
|
|
; SI: v_mul_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}}
|
|
; SI: v_mul_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}}
|
|
define amdgpu_kernel void @fmul_v4f64(ptr addrspace(1) %out, ptr addrspace(1) %in1,
|
|
ptr addrspace(1) %in2) {
|
|
%r0 = load <4 x double>, ptr addrspace(1) %in1
|
|
%r1 = load <4 x double>, ptr addrspace(1) %in2
|
|
%r2 = fmul <4 x double> %r0, %r1
|
|
store <4 x double> %r2, ptr addrspace(1) %out
|
|
ret void
|
|
}
|