9e9907f1cf
Similar to 806761a7629df268c8aed49657aeccffa6bca449. For IR files without a target triple, -mtriple= specifies the full target triple while -march= merely sets the architecture part of the default target triple, leaving a target triple which may not make sense, e.g. amdgpu-apple-darwin. Therefore, -march= is error-prone and not recommended for tests without a target triple. The issue has been benign as we recognize $unknown-apple-darwin as ELF instead of rejecting it outrightly. This patch changes AMDGPU tests to not rely on the default OS/environment components. Tests that need fixes are not changed: ``` LLVM :: CodeGen/AMDGPU/fabs.f64.ll LLVM :: CodeGen/AMDGPU/fabs.ll LLVM :: CodeGen/AMDGPU/floor.ll LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll LLVM :: CodeGen/AMDGPU/fneg-fabs.ll LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll LLVM :: CodeGen/AMDGPU/schedule-if-2.ll ```
70 lines
2.5 KiB
YAML
70 lines
2.5 KiB
YAML
# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -run-pass=si-fold-operands,dead-mi-elimination -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s
|
|
# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -run-pass=si-fold-operands,dead-mi-elimination -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s
|
|
|
|
# GCN-LABEL: name: fold_vgpr_to_vgpr_copy
|
|
# GCN: %0:vreg_64 = IMPLICIT_DEF
|
|
# GCN-NEXT: %1:vgpr_32 = IMPLICIT_DEF
|
|
# GCN-NEXT: %2:vgpr_32 = IMPLICIT_DEF
|
|
# GCN-NEXT: DS_WRITE2_B32_gfx9 %0.sub0, killed %1, killed %2, 0, 1, 0, implicit $exec
|
|
|
|
---
|
|
name: fold_vgpr_to_vgpr_copy
|
|
body: |
|
|
bb.0:
|
|
|
|
%0:vreg_64 = IMPLICIT_DEF
|
|
%4:vgpr_32 = IMPLICIT_DEF
|
|
%3:vgpr_32 = IMPLICIT_DEF
|
|
%1:vgpr_32 = COPY %0.sub0
|
|
%2:vgpr_32 = COPY %1
|
|
DS_WRITE2_B32_gfx9 %2, killed %4, killed %3, 0, 1, 0, implicit $exec
|
|
...
|
|
|
|
# GCN-LABEL: name: fold_sgpr_to_vgpr_copy
|
|
# GCN: %0:sreg_64 = IMPLICIT_DEF
|
|
# GCN-NEXT: %1:vgpr_32 = IMPLICIT_DEF
|
|
# GCN-NEXT: %2:vgpr_32 = IMPLICIT_DEF
|
|
# GCN-NEXT: %4:vgpr_32 = COPY %0.sub0
|
|
# GCN-NEXT: DS_WRITE2_B32_gfx9 %4, killed %1, killed %2, 0, 1, 0, implicit $exec
|
|
name: fold_sgpr_to_vgpr_copy
|
|
body: |
|
|
bb.0:
|
|
|
|
%0:sreg_64 = IMPLICIT_DEF
|
|
%4:vgpr_32 = IMPLICIT_DEF
|
|
%3:vgpr_32 = IMPLICIT_DEF
|
|
%1:sgpr_32 = COPY %0.sub0
|
|
%2:vgpr_32 = COPY %1
|
|
DS_WRITE2_B32_gfx9 %2, killed %4, killed %3, 0, 1, 0, implicit $exec
|
|
...
|
|
|
|
# GCN-LABEL: name: fma_sgpr_use
|
|
# GCN: %0:sreg_64_xexec = IMPLICIT_DEF
|
|
# GCN-NEXT: %4:vgpr_32 = nnan ninf nsz arcp contract afn reassoc V_FMA_F32_e64 2, %0.sub0, 0, 1073741824, 0, %0.sub1, 0, 0, implicit $mode, implicit $exec
|
|
---
|
|
name: fma_sgpr_use
|
|
body: |
|
|
bb.0:
|
|
%0:sreg_64_xexec = IMPLICIT_DEF
|
|
%1:sgpr_32 = COPY %0.sub0
|
|
%2:sgpr_32 = COPY %0.sub1
|
|
%3:vgpr_32 = COPY %2
|
|
%4:vgpr_32 = nnan ninf nsz arcp contract afn reassoc V_FMAC_F32_e64 2, %1, 0, 1073741824, 0, %3, 0, 0, implicit $mode, implicit $exec
|
|
DS_WRITE2_B32_gfx9 undef %5:vgpr_32, killed %4, undef %6:vgpr_32, 0, 1, 0, implicit $exec
|
|
...
|
|
|
|
# GCN-LABEL: name: fma_sgpr_sgpr_use
|
|
# GCN: %0:sgpr_32 = IMPLICIT_DEF
|
|
# GCN-NEXT: %2:vgpr_32 = V_MOV_B32_e32 1234567, implicit $exec
|
|
# GCN-NEXT: %3:vgpr_32 = V_FMAC_F32_e64 0, %0, 0, 1234567, 0, %2, 0, 0, implicit $mode, implicit $exec
|
|
---
|
|
name: fma_sgpr_sgpr_use
|
|
body: |
|
|
bb.0:
|
|
%0:sgpr_32 = IMPLICIT_DEF
|
|
%1:sgpr_32 = S_MOV_B32 1234567
|
|
%2:vgpr_32 = COPY %1
|
|
%3:vgpr_32 = V_FMAC_F32_e64 0, %0, 0, %1, 0, %2, 0, 0, implicit $mode, implicit $exec
|
|
S_ENDPGM 0, implicit %3
|
|
...
|