9e9907f1cf
Similar to 806761a7629df268c8aed49657aeccffa6bca449. For IR files without a target triple, -mtriple= specifies the full target triple while -march= merely sets the architecture part of the default target triple, leaving a target triple which may not make sense, e.g. amdgpu-apple-darwin. Therefore, -march= is error-prone and not recommended for tests without a target triple. The issue has been benign as we recognize $unknown-apple-darwin as ELF instead of rejecting it outrightly. This patch changes AMDGPU tests to not rely on the default OS/environment components. Tests that need fixes are not changed: ``` LLVM :: CodeGen/AMDGPU/fabs.f64.ll LLVM :: CodeGen/AMDGPU/fabs.ll LLVM :: CodeGen/AMDGPU/floor.ll LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll LLVM :: CodeGen/AMDGPU/fneg-fabs.ll LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll LLVM :: CodeGen/AMDGPU/schedule-if-2.ll ```
48 lines
1.8 KiB
LLVM
48 lines
1.8 KiB
LLVM
; RUN: llc -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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; RUN: llc -mtriple=amdgcn -mcpu=tonga -global-isel -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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declare i32 @llvm.amdgcn.perm(i32, i32, i32) #0
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; GCN-LABEL: {{^}}v_perm_b32_v_v_v:
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; GCN: v_perm_b32 v{{[0-9]+}}, v0, v1, v2
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define amdgpu_ps void @v_perm_b32_v_v_v(i32 %src1, i32 %src2, i32 %src3, ptr addrspace(1) %out) #1 {
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%val = call i32 @llvm.amdgcn.perm(i32 %src1, i32 %src2, i32 %src3) #0
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store i32 %val, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: {{^}}v_perm_b32_v_v_c:
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; GCN: v_perm_b32 v{{[0-9]+}}, v0, v1, {{[vs][0-9]+}}
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define amdgpu_ps void @v_perm_b32_v_v_c(i32 %src1, i32 %src2, ptr addrspace(1) %out) #1 {
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%val = call i32 @llvm.amdgcn.perm(i32 %src1, i32 %src2, i32 12345) #0
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store i32 %val, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: {{^}}v_perm_b32_s_v_c:
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; GCN: v_perm_b32 v{{[0-9]+}}, s0, v0, v{{[0-9]+}}
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define amdgpu_ps void @v_perm_b32_s_v_c(i32 inreg %src1, i32 %src2, ptr addrspace(1) %out) #1 {
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%val = call i32 @llvm.amdgcn.perm(i32 %src1, i32 %src2, i32 12345) #0
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store i32 %val, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: {{^}}v_perm_b32_s_s_c:
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; GCN: v_perm_b32 v{{[0-9]+}}, s0, v{{[0-9]+}}, v{{[0-9]+}}
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define amdgpu_ps void @v_perm_b32_s_s_c(i32 inreg %src1, i32 inreg %src2, ptr addrspace(1) %out) #1 {
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%val = call i32 @llvm.amdgcn.perm(i32 %src1, i32 %src2, i32 12345) #0
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store i32 %val, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: {{^}}v_perm_b32_v_s_i:
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; GCN: v_perm_b32 v{{[0-9]+}}, v0, s0, 1
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define amdgpu_ps void @v_perm_b32_v_s_i(i32 %src1, i32 inreg %src2, ptr addrspace(1) %out) #1 {
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%val = call i32 @llvm.amdgcn.perm(i32 %src1, i32 %src2, i32 1) #0
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store i32 %val, ptr addrspace(1) %out
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ret void
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}
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attributes #0 = { nounwind readnone }
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attributes #1 = { nounwind }
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