9e9907f1cf
Similar to 806761a7629df268c8aed49657aeccffa6bca449. For IR files without a target triple, -mtriple= specifies the full target triple while -march= merely sets the architecture part of the default target triple, leaving a target triple which may not make sense, e.g. amdgpu-apple-darwin. Therefore, -march= is error-prone and not recommended for tests without a target triple. The issue has been benign as we recognize $unknown-apple-darwin as ELF instead of rejecting it outrightly. This patch changes AMDGPU tests to not rely on the default OS/environment components. Tests that need fixes are not changed: ``` LLVM :: CodeGen/AMDGPU/fabs.f64.ll LLVM :: CodeGen/AMDGPU/fabs.ll LLVM :: CodeGen/AMDGPU/floor.ll LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll LLVM :: CodeGen/AMDGPU/fneg-fabs.ll LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll LLVM :: CodeGen/AMDGPU/schedule-if-2.ll ```
67 lines
2.4 KiB
LLVM
67 lines
2.4 KiB
LLVM
; RUN: llc -mtriple=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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declare float @llvm.amdgcn.rsq.f32(float) #0
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declare double @llvm.amdgcn.rsq.f64(double) #0
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; FUNC-LABEL: {{^}}rsq_f32:
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; SI: v_rsq_f32_e32 {{v[0-9]+}}, {{s[0-9]+}}
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define amdgpu_kernel void @rsq_f32(ptr addrspace(1) %out, float %src) #1 {
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%rsq = call float @llvm.amdgcn.rsq.f32(float %src) #0
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store float %rsq, ptr addrspace(1) %out, align 4
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ret void
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}
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; TODO: Really these should be constant folded
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; FUNC-LABEL: {{^}}rsq_f32_constant_4.0
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; SI: v_rsq_f32_e32 {{v[0-9]+}}, 4.0
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define amdgpu_kernel void @rsq_f32_constant_4.0(ptr addrspace(1) %out) #1 {
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%rsq = call float @llvm.amdgcn.rsq.f32(float 4.0) #0
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store float %rsq, ptr addrspace(1) %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}rsq_f32_constant_100.0
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; SI: v_rsq_f32_e32 {{v[0-9]+}}, 0x42c80000
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define amdgpu_kernel void @rsq_f32_constant_100.0(ptr addrspace(1) %out) #1 {
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%rsq = call float @llvm.amdgcn.rsq.f32(float 100.0) #0
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store float %rsq, ptr addrspace(1) %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}rsq_f64:
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; SI: v_rsq_f64_e32 {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
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define amdgpu_kernel void @rsq_f64(ptr addrspace(1) %out, double %src) #1 {
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%rsq = call double @llvm.amdgcn.rsq.f64(double %src) #0
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store double %rsq, ptr addrspace(1) %out, align 4
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ret void
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}
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; TODO: Really these should be constant folded
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; FUNC-LABEL: {{^}}rsq_f64_constant_4.0
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; SI: v_rsq_f64_e32 {{v\[[0-9]+:[0-9]+\]}}, 4.0
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define amdgpu_kernel void @rsq_f64_constant_4.0(ptr addrspace(1) %out) #1 {
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%rsq = call double @llvm.amdgcn.rsq.f64(double 4.0) #0
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store double %rsq, ptr addrspace(1) %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}rsq_f64_constant_100.0
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; SI: v_rsq_f64_e32 {{v\[[0-9]+:[0-9]+\]}}, 0x40590000
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define amdgpu_kernel void @rsq_f64_constant_100.0(ptr addrspace(1) %out) #1 {
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%rsq = call double @llvm.amdgcn.rsq.f64(double 100.0) #0
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store double %rsq, ptr addrspace(1) %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}rsq_undef_f32:
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; SI-NOT: v_rsq_f32
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define amdgpu_kernel void @rsq_undef_f32(ptr addrspace(1) %out) #1 {
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%rsq = call float @llvm.amdgcn.rsq.f32(float undef)
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store float %rsq, ptr addrspace(1) %out, align 4
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ret void
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}
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attributes #0 = { nounwind readnone }
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attributes #1 = { nounwind }
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