9e9907f1cf
Similar to 806761a7629df268c8aed49657aeccffa6bca449. For IR files without a target triple, -mtriple= specifies the full target triple while -march= merely sets the architecture part of the default target triple, leaving a target triple which may not make sense, e.g. amdgpu-apple-darwin. Therefore, -march= is error-prone and not recommended for tests without a target triple. The issue has been benign as we recognize $unknown-apple-darwin as ELF instead of rejecting it outrightly. This patch changes AMDGPU tests to not rely on the default OS/environment components. Tests that need fixes are not changed: ``` LLVM :: CodeGen/AMDGPU/fabs.f64.ll LLVM :: CodeGen/AMDGPU/fabs.ll LLVM :: CodeGen/AMDGPU/floor.ll LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll LLVM :: CodeGen/AMDGPU/fneg-fabs.ll LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll LLVM :: CodeGen/AMDGPU/schedule-if-2.ll ```
24 lines
854 B
LLVM
24 lines
854 B
LLVM
; RUN: llc -mtriple=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,MOVREL %s
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; RUN: llc -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,MOVREL %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GPRIDX %s
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; GCN-LABEL: {{^}}main:
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; MOVREL: s_mov_b32 m0, s0
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; MOVREL-NEXT: v_movreld_b32_e32 v0,
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; GPRIDX: s_set_gpr_idx_on s0, gpr_idx(DST)
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; GPRIDX-NEXT: v_mov_b32_e32 v0, 1.0
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; GPRIDX-NEXT: s_set_gpr_idx_off
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; GCN-NEXT: v_mov_b32_e32 v0, v1
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; GCN-NEXT: ; return
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define amdgpu_ps float @main(i32 inreg %arg) #0 {
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main_body:
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%tmp24 = insertelement <16 x float> zeroinitializer, float 1.000000e+00, i32 %arg
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%tmp25 = extractelement <16 x float> %tmp24, i32 1
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ret float %tmp25
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}
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attributes #0 = { "InitialPSInputAddr"="36983" }
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