9e9907f1cf
Similar to 806761a7629df268c8aed49657aeccffa6bca449. For IR files without a target triple, -mtriple= specifies the full target triple while -march= merely sets the architecture part of the default target triple, leaving a target triple which may not make sense, e.g. amdgpu-apple-darwin. Therefore, -march= is error-prone and not recommended for tests without a target triple. The issue has been benign as we recognize $unknown-apple-darwin as ELF instead of rejecting it outrightly. This patch changes AMDGPU tests to not rely on the default OS/environment components. Tests that need fixes are not changed: ``` LLVM :: CodeGen/AMDGPU/fabs.f64.ll LLVM :: CodeGen/AMDGPU/fabs.ll LLVM :: CodeGen/AMDGPU/floor.ll LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll LLVM :: CodeGen/AMDGPU/fneg-fabs.ll LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll LLVM :: CodeGen/AMDGPU/schedule-if-2.ll ```
97 lines
2.3 KiB
YAML
97 lines
2.3 KiB
YAML
# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass=si-fix-sgpr-copies -o - %s | FileCheck -check-prefix=GCN %s
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---
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# GCN-LABEL: name: phi_moveimm_input
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# GCN-NOT: %{{[0-9]+}}:vgpr_32 = PHI %{{[0-9]+}}, %bb.3, %{{[0-9]+}}, %bb.1
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# GCN: %{{[0-9]+}}:sreg_32 = PHI %{{[0-9]+}}, %bb.3, %{{[0-9]+}}, %bb.1
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name: phi_moveimm_input
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tracksRegLiveness: true
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body: |
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bb.0:
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successors: %bb.1
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liveins: $sgpr0, $sgpr1
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%0:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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%4:sreg_32 = COPY $sgpr0
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%5:sreg_32 = COPY $sgpr1
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bb.1:
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successors: %bb.2
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%2:sreg_32 = S_ADD_U32 %4, %5, implicit-def $scc
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S_BRANCH %bb.2
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bb.2:
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successors: %bb.3
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%3:sreg_32 = PHI %1, %bb.3, %2, %bb.1
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S_BRANCH %bb.3
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bb.3:
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successors: %bb.2
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%1:sreg_32 = COPY %0
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S_BRANCH %bb.2
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...
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---
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# GCN-LABEL: name: phi_moveimm_subreg_input
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# GCN: %{{[0-9]+}}:sreg_64 = PHI %{{[0-9]+}}, %bb.3, %{{[0-9]+}}, %bb.1
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name: phi_moveimm_subreg_input
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tracksRegLiveness: true
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body: |
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bb.0:
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successors: %bb.1
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liveins: $sgpr0, $sgpr1
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%0:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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%4:sreg_32 = COPY $sgpr0
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%5:sreg_32 = COPY $sgpr1
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bb.1:
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successors: %bb.2
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undef %2.sub0:sreg_64 = S_ADD_U32 %4, %5, implicit-def $scc
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S_BRANCH %bb.2
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bb.2:
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successors: %bb.3
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%3:sreg_64 = PHI %1, %bb.3, %2, %bb.1
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S_BRANCH %bb.3
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bb.3:
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successors: %bb.2
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undef %1.sub0:sreg_64 = COPY %0
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S_BRANCH %bb.2
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...
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---
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# GCN-LABEL: name: phi_moveimm_bad_opcode_input
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# GCN-NOT: %{{[0-9]+}}:sreg_32 = PHI %{{[0-9]+}}, %bb.3, %{{[0-9]+}}, %bb.1
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# GCN: %{{[0-9]+}}:vgpr_32 = PHI %{{[0-9]+}}, %bb.3, %{{[0-9]+}}, %bb.1
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name: phi_moveimm_bad_opcode_input
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tracksRegLiveness: true
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body: |
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bb.0:
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successors: %bb.1
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liveins: $sgpr0, $sgpr1, $vgpr0
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%6:vgpr_32 = COPY $vgpr0
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%0:vgpr_32 = V_MOV_B32_sdwa 0, %6:vgpr_32, 0, 5, 2, 4, implicit $exec, implicit %6:vgpr_32(tied-def 0)
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%4:sreg_32 = COPY $sgpr0
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%5:sreg_32 = COPY $sgpr1
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bb.1:
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successors: %bb.2
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%2:sreg_32 = S_ADD_U32 %4, %5, implicit-def $scc
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S_BRANCH %bb.2
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bb.2:
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successors: %bb.3
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%3:sreg_32 = PHI %1, %bb.3, %2, %bb.1
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S_BRANCH %bb.3
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bb.3:
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successors: %bb.2
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%1:sreg_32 = COPY %0
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S_BRANCH %bb.2
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...
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