9e9907f1cf
Similar to 806761a7629df268c8aed49657aeccffa6bca449. For IR files without a target triple, -mtriple= specifies the full target triple while -march= merely sets the architecture part of the default target triple, leaving a target triple which may not make sense, e.g. amdgpu-apple-darwin. Therefore, -march= is error-prone and not recommended for tests without a target triple. The issue has been benign as we recognize $unknown-apple-darwin as ELF instead of rejecting it outrightly. This patch changes AMDGPU tests to not rely on the default OS/environment components. Tests that need fixes are not changed: ``` LLVM :: CodeGen/AMDGPU/fabs.f64.ll LLVM :: CodeGen/AMDGPU/fabs.ll LLVM :: CodeGen/AMDGPU/floor.ll LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll LLVM :: CodeGen/AMDGPU/fneg-fabs.ll LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll LLVM :: CodeGen/AMDGPU/schedule-if-2.ll ```
50 lines
1.6 KiB
LLVM
50 lines
1.6 KiB
LLVM
; RUN: llc -mtriple=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VCCZ-BUG %s
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; RUN: llc -mtriple=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VCCZ-BUG %s
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; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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; GCN-LABEL: {{^}}vccz_workaround:
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; GCN: s_load_dword [[REG:s[0-9]+]], s[{{[0-9]+:[0-9]+}}],
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; GCN: v_cmp_neq_f32_e64 {{[^,]*}}, [[REG]], 0{{$}}
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; VCCZ-BUG: s_waitcnt lgkmcnt(0)
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; VCCZ-BUG: s_mov_b64 vcc, vcc
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; GCN-NOT: s_mov_b64 vcc, vcc
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; GCN: s_cbranch_vccnz [[EXIT:.L[0-9A-Za-z_]+]]
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; GCN: buffer_store_dword
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; GCN: [[EXIT]]:
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; GCN: s_endpgm
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define amdgpu_kernel void @vccz_workaround(ptr addrspace(4) %in, ptr addrspace(1) %out, float %cond) {
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entry:
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%cnd = fcmp oeq float 0.0, %cond
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%sgpr = load volatile i32, ptr addrspace(4) %in
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br i1 %cnd, label %if, label %endif
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if:
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store i32 %sgpr, ptr addrspace(1) %out
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br label %endif
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endif:
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ret void
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}
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; GCN-LABEL: {{^}}vccz_noworkaround:
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; GCN: v_cmp_neq_f32_e32 vcc, 0, v{{[0-9]+}}
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; GCN-NOT: s_waitcnt lgkmcnt(0)
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; GCN-NOT: s_mov_b64 vcc, vcc
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; GCN: s_cbranch_vccnz [[EXIT:.L[0-9A-Za-z_]+]]
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; GCN: buffer_store_dword
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; GCN: [[EXIT]]:
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; GCN: s_endpgm
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define amdgpu_kernel void @vccz_noworkaround(ptr addrspace(1) %in, ptr addrspace(1) %out) {
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entry:
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%vgpr = load volatile float, ptr addrspace(1) %in
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%cnd = fcmp oeq float 0.0, %vgpr
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br i1 %cnd, label %if, label %endif
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if:
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store float %vgpr, ptr addrspace(1) %out
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br label %endif
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endif:
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ret void
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}
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