9e9907f1cf
Similar to 806761a7629df268c8aed49657aeccffa6bca449. For IR files without a target triple, -mtriple= specifies the full target triple while -march= merely sets the architecture part of the default target triple, leaving a target triple which may not make sense, e.g. amdgpu-apple-darwin. Therefore, -march= is error-prone and not recommended for tests without a target triple. The issue has been benign as we recognize $unknown-apple-darwin as ELF instead of rejecting it outrightly. This patch changes AMDGPU tests to not rely on the default OS/environment components. Tests that need fixes are not changed: ``` LLVM :: CodeGen/AMDGPU/fabs.f64.ll LLVM :: CodeGen/AMDGPU/fabs.ll LLVM :: CodeGen/AMDGPU/floor.ll LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll LLVM :: CodeGen/AMDGPU/fneg-fabs.ll LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll LLVM :: CodeGen/AMDGPU/schedule-if-2.ll ```
25 lines
1.3 KiB
LLVM
25 lines
1.3 KiB
LLVM
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,NO-ECC %s
|
|
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -mattr=+sramecc < %s | FileCheck -check-prefixes=GCN,NO-ECC %s
|
|
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -mattr=-sramecc < %s | FileCheck -check-prefixes=GCN,NO-ECC %s
|
|
; RUN: llc -mtriple=amdgcn -mcpu=gfx902 -mattr=+sramecc < %s | FileCheck -check-prefixes=GCN,NO-ECC %s
|
|
; RUN: llc -mtriple=amdgcn -mcpu=gfx904 -mattr=+sramecc < %s | FileCheck -check-prefixes=GCN,NO-ECC %s
|
|
; RUN: llc -mtriple=amdgcn -mcpu=gfx906 -mattr=+sramecc < %s | FileCheck -check-prefixes=GCN,ECC %s
|
|
; RUN: llc -mtriple=amdgcn -mcpu=gfx906 -mattr=-sramecc < %s | FileCheck -check-prefixes=GCN,NO-ECC %s
|
|
|
|
; Make sure the correct set of targets are marked with
|
|
; FeatureDoesNotSupportSRAMECC, and +sramecc is ignored if it's never
|
|
; supported.
|
|
|
|
; GCN-LABEL: {{^}}load_global_hi_v2i16_reglo_vreg:
|
|
; NO-ECC: global_load_short_d16_hi
|
|
; ECC: global_load_ushort
|
|
define void @load_global_hi_v2i16_reglo_vreg(ptr addrspace(1) %in, i16 %reg) {
|
|
entry:
|
|
%gep = getelementptr inbounds i16, ptr addrspace(1) %in, i64 -2047
|
|
%load = load i16, ptr addrspace(1) %gep
|
|
%build0 = insertelement <2 x i16> undef, i16 %reg, i32 0
|
|
%build1 = insertelement <2 x i16> %build0, i16 %load, i32 1
|
|
store <2 x i16> %build1, ptr addrspace(1) undef
|
|
ret void
|
|
}
|