a5c90e48b6
The SelectionDAG scheduling preference now becomes source order scheduling (machine scheduler generates better code -- even without there being a machine model defined for LoongArch yet). Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact. This is similar to commit: 3d0fbafd0bce43bb9106230a45d1130f7a40e5ec
35 lines
1.0 KiB
LLVM
35 lines
1.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
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; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
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define void @fsub_v4f32(ptr %res, ptr %a0, ptr %a1) nounwind {
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; CHECK-LABEL: fsub_v4f32:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vld $vr0, $a1, 0
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; CHECK-NEXT: vld $vr1, $a2, 0
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; CHECK-NEXT: vfsub.s $vr0, $vr0, $vr1
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; CHECK-NEXT: vst $vr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <4 x float>, ptr %a0
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%v1 = load <4 x float>, ptr %a1
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%v2 = fsub <4 x float> %v0, %v1
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store <4 x float> %v2, ptr %res
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ret void
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}
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define void @fsub_v2f64(ptr %res, ptr %a0, ptr %a1) nounwind {
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; CHECK-LABEL: fsub_v2f64:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vld $vr0, $a1, 0
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; CHECK-NEXT: vld $vr1, $a2, 0
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; CHECK-NEXT: vfsub.d $vr0, $vr0, $vr1
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; CHECK-NEXT: vst $vr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <2 x double>, ptr %a0
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%v1 = load <2 x double>, ptr %a1
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%v2 = fsub <2 x double> %v0, %v1
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store <2 x double> %v2, ptr %res
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ret void
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}
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